F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

5.2. Clock Connections in Multiple Instance Operation

This clock connection describes multiple IP core instantiations in your design.

This is a recommended clocking for multiple IP core clock connections.

You must make the following clock connections:
  • The i_clk_ref and the i_clk_sys clocks drives all instantiated IP cores.
  • The output clock o_clk_pll of a single IP core can drive all instantiated IP core i_clk_rx and the i_clk_tx input signals under the following conditions:
    • The shared clock is traceable to a common source reference clock.
    • The F-Tile Ethernet Intel® FPGA Hard IP uses the same rate to configure the its port system clocks.
Figure 22. Clock Connections for Multiple IP Cores
The following are examples of alternative clock sources satisfying the clock connections requirements:
  • Another IP instance's o_clk_pll output clock can drive an IP core specific i_clk_rx and the i_clk_tx input signals provided that their respective reference clocks are configured at the same rate.
  • An IO PLL can drive an IP core related input clock signals provided that the PLL and IP core derive their i_clk_ref reference clock from the same reference clock source.
  • A GPIO, directly connected to the reference clock, with frequency of 161.1328125 MHz, can directly drive the i_clk_rx and the i_clk_tx input signals.