F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents

2.4.1. Generating IP-XACT File

You can generate the IP-XACT information for the F-Tile Ethernet Intel® FPGA Hard IP. This IP-XACT information is included in the <ip_name>.ip file. The generated IP-XACT information includes the register map for your IP. It contains generic information about your IP. The IP variant-specific information such as reset and some register values may vary across the IP variants.

Use the following steps to enable IP-XACT generation in the <ip_name>.ip file:
  1. In the IP Parameter Editor window, click Generate HDL.
  2. In the Generation dialog box, select the IP-XACT setting.
  3. Click Generate.
  4. Check your <ip_name>.ip file for the IP-XACT information.

Generating IP-XACT Files for Designs with enabled PTP

When you select Enable IEEE 1588 PTP setting in the IP Parameter Editor, the PTP-specific registers information is available as follows:
  • PTP-related registers are IP-specific. These registers are available in the F-Tile Ethernet Intel® FPGA Hard IP's generated .ipxact file.
  • PTP asymmetry delay registers and P2P delay registers are tile-specific, not IP-specific registers.

    In the Generation dialog box, ensure the Create HDL design files for synthesis parameter is set to Verilog or VHDL.

    The IP synthesis file directory contains the generated .xml files:
    • <variant_name>/eth_f_<version>/synth/eth_ptp_adpt_f_p2p_ipxact.xml
    • <variant_name>/eth_f_<version>/synth/eth_ptp_adpt_f_asm_ipxact.xml