F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
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7.11. Custom Rate Interface

The F-Tile Ethernet Intel® FPGA Hard IP Custom Rate Interface is available when you enable Use external custom cadence controller option. The interface accounts for differences between the system clock and the TX transceiver PLL rate.

Table 55.  Signals of the Custom Rate InterfaceAll of the Custom Rate Interface signals except the i_custom_cadence signal are asynchronous.

Signal Name

Width

Description

i_custom_cadence 1

Custom data valid signal.

  • 1'b1: Set cadence data valid high for this cycle
  • 1'b0: Set cadence data valid low for this cycle

Connect this signal either to a counter that produces a steady data valid cadence that corresponds to the ratio between the clock rate used and the clock rate required, or a system that increases or decreases the data valid cadence based on the current occupancy of transceiver TX FIFO or an external TX FIFO.

Note: The TX reset sequence requires valid custom cadence pulses. You must start driving i_custom_cadence before o_tx_lanes_stable assert. You may drive i_custom_cadence as soon as o_tx_pll_locked asserts, and any external cadence generation logic and clocks are out of reset.
Figure 53. Custom rate Interface Behavior with a Fixed Data Valid Ratio

A counter producing a steady ratio of high and low pulses to balance the flow through a channel can drive the custom cadence rate interface.