F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 3/11/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.2.3. PTP Asymmetry Delay Reconfiguration Interface

Table 78.  PTP Asymmetry Reconfiguration InterfaceThe signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal of the PTP tile adapter. This clock and reset are used for all the reconfiguration interfaces in the IP core.
Port Name Width Description

i_reconfig_ptp_asym_addr[16:0]

17 bits

Word address bus for PTP asymmetry delay and status registers.

i_reconfig_ptp_asym_read

1 bit

Read request signal for PTP asymmetry delay and status registers.

i_reconfig_ptp_asym_write

1 bit

Write request signal for PTP asymmetry delay and status registers.

i_reconfig_ptp_asym_byteenable[3:0]

4 bits

Byte enable for PTP asymmetry read and write request signals.

o_reconfig_ptp_asym_readdata[31:0]

32 bits

Read data from reads to PTP asymmetry delay and status registers.

o_reconfig_ptp_asym_readdata_valid

1 bit

When set, read data from PTP asymmetry delay and status registers is valid.

i_reconfig_ptp_asym_writedata[31:0]

32 bits

Write data for PTP asymmetry delay and status registers.

o_reconfig_ptp_asym_waitrequest

1 bit

Avalon® memory-mapped interface stalling signal for operations on PTP asymmetry delay and status registers.