F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
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5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation

When you enable Enable IEEE 1588 PTP in your IP, all Ethernet IP cores must be clocked by the same system clock source o_clk_pll of the PTP tile adapter. The required input clock source is system clock source divided by 2, with a minimum frequency of 402.83 MHz.

When you enable Enable asynchronous adapter clocks along with the Enable IEEE 1588 PTP in your IP, the i_clk_pll signal must connect to the same system clock source. The i_clk_tx and i_clk_rx input clock signals can be asynchronous from each other and from o_clk_pll clock provided that the clocks are fast enough to ensure the IP core channel processes all data.

The PTP tile adapter's i_sys_clk clock is sourced from its own o_clk_pll clock.

Figure 24. Clock Connections in PTP-Based Synchronous and Asynchronous Operation