JESD204B Intel® FPGA IP Core – Support Center

Welcome to the JESD204B Intel® FPGA IP core support center!

Here you will find information on how to select, design, and implement JESD204B links. There are also guidelines on how to bring up your system and debug the JESD204B links. This page is organized into categories that align with a JESD204B system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

Which Intel® FPGA Family Should I Use?

Table 1 - JESD204B Intel^® FPGA IP Core Performance
Device Family	PMA Speed Grade	FPGA Fabric Speed Grade	Data Rate		Link Clock f_MAX(MHz)
Device Family	PMA Speed Grade	FPGA Fabric Speed Grade	Enable Hard PCS (Gbps)	Enable Soft PCS (Gbps) ¹	Link Clock f_MAX(MHz)
Intel® Agilex™ (E-Tile)	2	-2	Not supported	2.0 to 17.4	data_rate/40
	3	-2	Not supported	2.0 to 17.4	data_rate/40
	3	-3	Not supported	2.0 to 16.0	data_rate/40
Intel® Stratix^® 10 (L-Tile and H-Tile)	1	1	2.0 to 12.0	2.0 to 16.0²	data_rate/40
	1	2	2.0 to 12.0	2.0 to 14.0	data_rate/40
	2	1	2.0 to 9.83	2.0 to 16.0²	data_rate/40
	2	2	2.0 to 9.83	2.0 to 14.0	data_rate/40
	3	1	2.0 to 9.83	2.0 to 16.0²	data_rate/40
		2	2.0 to 9.83	2.0 to 14.0	data_rate/40
		3	2.0 to 9.83	2.0 to 13.0	data_rate/40
Intel® Stratix® 10 (E-Tile)	1	1	Not supported	2.0 to 16.0²	data_rate/40
	1	2	Not supported	2.0 to 14.0	data_rate/40
	2	1	Not supported	2.0 to 16.0²	data_rate/40
	2	2	Not supported	2.0 to 14.0	data_rate/40
	3	3	Not supported	2.0 to 13.0	data_rate/40
Intel® Arria^® 10	1	1	2.0 to 12.0	2.0 to 15.0 ² ³	data rate/40
	2	1	2.0 to 12.0	2.0 to 15.0 ² ³	data rate/40
	2	2	2.0 to 9.83	2.0 to 15.0 ² ³	data rate/40
	3	1	2.0 to 12.0	2.0 to 14.2 ² ⁴	data rate/40
	3	2	2.0 to 9.83	2.0 to 14.2 ² ⁵	data rate/40
	4	3	2.0 to 8.83	2.0 to 12.5⁶	data rate/40
Intel® Cyclone^® 10 GX	<Any supported speed grade>	<Any supported speed grade>	2.0 to 6.25	2.0 to 6.25	data rate/40

1. Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional 10–20% increase in resource utilization^†.

2. Refer to the Intel Arria 10 and Intel Stratix 10 Device Datasheet for the maximum data rate supported across transceiver speed grades and transceiver power supply operating conditions.

3. When using Soft PCS mode at 15.0 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.

4. For Intel Arria 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is up to 12.288 Gbps.

5. For Intel Arria 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 11.0 Gbps.

6. For Intel Arria 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 10.0 Gbps.

Additional Resources

Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 Devices

JESD204B Intel® FPGA IP User Guide (HTML | PDF)
JESD204B Intel® Agilex™ FPGA IP Design Example User Guide (HTML | PDF)
JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide (HTML | PDF)
JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide (HTML | PDF)
JESD204B Intel® Cyclone® 10 FPGA IP Design Example User Guide (HTML | PDF)
E-Tile Transceiver PHY User Guide (HTML | PDF)
Intel® Arria® 10 Transceiver PHY User Guide (HTML | PDF)
L- and H-Tile Transceiver PHY User Guide (HTML | PDF)
Intel Cyclone 10 GX Transceiver PHY User Guide (HTML | PDF)

Where Can I Find Information on IP integration?

Intel® Agilex™ Devices

AN 901: Implementing Synchronized ADC-Agilex E-Tile Dual Link Design with JESD204C RX IP Core (HTML | PDF)

Intel® Stratix® 10 Devices

AN804: Implementing Synchronized ADC Multi-link Designs with Intel Stratix 10 JESD204B RX IP Core (HTML | PDF)
AN804: Implementing Unsynchronized ADC Multi-link Designs with Intel Stratix 10 JESD204B RX IP Core (HTML | PDF)

Intel Arria® 10 Devices

AN803: Implementing Synchronized ADC Multi-link Designs with Intel Arria 10 JESD204B RX IP Core (HTML | PDF)
AN803: Implementating Unsynchronized ADC Multi-link Designs with Intel Arria 10 JESD204B RX IP Core (HTML | PDF)

Pin Connection Guidelines

Intel® Agilex™ Devices

Intel Agilex Device Family Pin Connection Guidelines

Intel® Stratix® 10 Devices

Intel Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines

Intel® Arria® 10 Devices

Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel® Cyclone® 10 Devices

Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Schematic Review

Intel® Agilex™ Devices

Intel Agilex Device Schematic Review Worksheet

Intel® Stratix® 10 Devices

Intel Stratix 10 GX, MX, and SX Schematic Review Worksheet

Intel Arria® 10 Devices

Intel Arria 10 GX, GT, and SX Schematic Review Worksheet

Intel Cyclone® 10 Devices

Intel Cyclone 10 GX Schematic Review Worksheet

Board Design Guidelines

Power Management

Thermal Power Management

Intel® Agilex™ Devices

AN 944: Thermal Modeling for Intel Agilex FPGAs with the Intel FPGA Power and Thermal Calculator (HTML | PDF)

Intel® Stratix® 10 Devices

AN 787: Intel Stratix 10 Thermal Modeling and Management (HTML | PDF)

Power Sequencing

Intel® Agilex™ , Intel® Stratix® 10, Intel® Cyclone® 10, and Intel® Arria® 10 Devices

AN 692: Power Sequencing Considerations for Intel® Cyclone 10 GX, Intel® Arria® 10, Intel Stratix® 10, and Intel® Agilex™ Devices (HTML | PDF)

JESD204B Intel FPGA IP Hardware Checkout Reports

Intel® Agilex™ Devices

AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices (HTML | PDF)

Intel® Stratix® 10 Devices

AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices (HTML | PDF)
AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices (HTML | PDF)

Intel® Arria® 10 Devices

AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report (HTML | PDF)
AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report (HTML | PDF)
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report (HTML | PDF)
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report (HTML | PDF)
AN 779: Altera JESD204B IP Core and ADI AD9691 Hardware Checkout Report (HTML | PDF)
AN 785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report (HTML | PDF)
AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report (HTML | PDF)
AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report (HTML | PDF)

Design Examples and Reference Designs

Intel® Agilex™ Devices

AN 901: Implementing Synchronized ADC-Agilex E-Tile Dual Link Design with JESD204C RX IP Core (HTML | PDF)

Intel® Stratix® 10 Devices

AN 833: Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design (HTML | PDF)
AN 804: Implementing ADC-Stratix 10 Multi-Link Design with JESD204B RX IP (HTML | PDF)

Intel® Arria® 10 Devices

Intel Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design User Guide (HTML)
AN 729: Implementing JESD204B IP Core System Reference Design with Nios® II Processor (HTML | PDF)
AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design (HTML | PDF)
AN 803: Implementing Synchronized ADC-Arria 10 Multi-Link Design with JESD204B RX IP Core (HTML | PDF)

Additional Resources

General

JESD204B IP Core Design Example User Guide

Intel® Stratix® 10 Devices

JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

Intel® Arria® 10 Devices

JESD204B Intel Arria 10 FPGA IP Design Example User Guide

Intel® Cyclone® 10 Devices

JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide

Recommended Training Courses

Title	Type	Description
JESD204B MegaCore IP Overview	Online	This online course provides a broad overview of the JESD204B Intel FPGA IP core. For better understanding of all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification, and followed by a presentation of some of the important features of the JESD204B Intel FPGA IP core. Finally, a data flow of the system is used to describe the functional details of the core.

Title	Description
Arria® 10 interface to ADI 9144 using JESD204B IP	Learn about the interoperability of JESD204B Intel FPGA IP core on the Intel® Arria® 10 FPGA with the AD9144 converter from Analog Devices Inc. (ADI).
How to interoperate ADI AD9680 with Altera® JESD204B IP Core on Stratix® V FPGA	Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B Intel FPGA IP core.
How to interoperate ADI AD9680 with Altera JESD204B IP on Stratix V	Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B Intel FPGA IP core.
How to interoperate TI DAC37J84 with Altera JESD204B MegaCore on Stratix V FPGA	Learn about the interoperability of JESD204B Intel FPGA IP core on the Stratix® V FPGA with the DAC37J84 converter from Texas Instruments.
JESD204B Intel FPGA IP Quick Start Video	Learn about JESD204B standard and the JESD204B Intel FPGA IP solution. Find out how you can easily create a design example that works on hardware.
JESD204B Intel FPGA IP Demonstration	Learn about the interoperability of JESD204B Intel FPGA IP core on the Arria V FPGA with the DAC37J84 converter from Texas Instruments.
JESD204B Intel FPGA IP Quick Start Video	Learn about JESD204B standard and the JESD204B Intel FPGA IP solution. Find out how you can easily create a design example that works on hardware.