GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

2.2.2. Use Scenario Rules

There are design rules that you must follow for the use scenarios described in the table below:
Table 4.  Design Rules Associated With Specific Use Scenarios
Use Scenarios Design Rules
Multiple interfaces within a GTS transceiver bank using the FEC block 7 All FEC enabled interfaces within a GTS transceiver bank must be clocked by the same system PLL.
Independent simplex TX and simplex RX interfaces placed in same channel (dual simplex mode) 8 Both TX and RX interfaces:
  • If not using PMA clocking, must be clocked by the same System PLL.
  • Must share one Avalon® memory-mapped interface to access the channel. Enable arbiter logic if you need independent Avalon® memory-mapped interface access to the simplex TX and simplex RX interfaces placed in same channel.
  • Must enable FEC with the same configuration, if enabled in either the TX or RX interfaces.
Multiple lanes bonded to single link When bonded channels use a system PLL, they must all use the same system PLL.
7 Refer to FEC Architecture for details of the FEC core.
8 Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for the protocol IPs that support dual simplex mode and the implementation flow.