GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

2.5. Forward Error Correction (FEC) Architecture

The FEC block is located between the PCS and PMA interface. Each FEC core can be used to implement multiple FEC modes as shown in the following table.
Table 9.  Supported FEC Modes and Compliance Specifications
FEC Mode Specification FEC Compliance Specification
Firecode IEEE IEEE 802.3 BASE-R Firecode (CL 74)
RS-FEC IEEE IEEE 802.3 RS(528, 514) (CL 108)
ETC ETC RS(528, 514)
Note: You can use the FEC mode for the entire range of line rates from 1 Gbps to the transceiver maximum supported data rate for custom applications. If your configuration has multiple interfaces in one FEC block, the block must be clocked by the same system PLL and requires custom cadence. Refer to Datapath Clock Cadences for details.