GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

4. Implementing the GTS System PLL Clocks IP

The GTS System PLL Clocks IP is a required IP for the GTS PMA/FEC Direct PHY IP when the datapath clocking uses the system PLL. Other protocol IPs that use system PLL clocking also require this IP. This IP is also required if you use the system PLL as a PLL resource for the FPGA core fabric..

GTS System PLL Clocks IP Overview

The GTS System PLL Clocks IP performs the function described below:
  • Configures the system PLL:
    • Enable system PLL and specify the mode
    • Specifies the output and reference clock of the system PLL
This IP does not configure the IOPLL that can be used as a second system PLL in devices with a single transceiver bank. Refer to Clocking and PLL User Guide: Agilex® 3 FPGAs and SoCs for more information.