LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 844310
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Pro Edition Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1.4.4.9. Default I/O Frame

The default I/O frame is utilized in the LTPI operational mode to tunnel the LTPI channels.

It serves as a basic I/O frame format with predefined channel allocation according to the DC-SCM LTPI standard. Any of the channels are optional to be disabled. The sequence mapping of the enabled channels is fixed and cannot be rearranged during IP generation.

Table 24.  LTPI GPIO Channel Encoding
Name Bit Field Encoding
7 6 5 4 3 2 1 0
Low latency (LL) GPIO

LL GPIO7

  • 0: Low
  • 1: High

LL GPIO6

  • 0: Low
  • 1: High

LL GPIO5

  • 0: Low
  • 1: High

LL GPIO4

  • 0: Low
  • 1: High

LL GPIO3

  • 0: Low
  • 1: High

LL GPIO2

  • 0: Low
  • 1: High

LL GPIO1

  • 0: Low
  • 1: High

LL GPIO0

  • 0: Low
  • 1: High
Normal latency (NL) GPIO

NL GPIO [X+7]

  • 0: Low
  • 1: High

NL GPIO [X+6]

  • 0: Low
  • 1: High

NL GPIO [X+5]

  • 0: Low
  • 1: High

NL GPIO [X+4]

  • 0: Low
  • 1: High

NL GPIO [X+3]

  • 0: Low
  • 1: High

NL GPIO [X+2]

  • 0: Low
  • 1: High

NL GPIO [X+1]

  • 0: Low
  • 1: High

NL GPIO [X]

  • 0: Low
  • 1: High
Table 25.  UART Channel Encoding
Name Bit Field Encoding
7 6 5 4 3 2 1 0
UART0/1 TX Encoding UART1 UART0

RTS

  • 0: Low
  • 1: High

TXD[2]

  • 0: Low
  • 1: High

TXD[1]

  • 0: Low
  • 1: High

TXD[0]

  • 0: Low
  • 1: High

RTS

  • 0: Low
  • 1: High

TXD[2]

  • 0: Low
  • 1: High

TXD[1]

  • 0: Low
  • 1: High

TXD[0]

  • 0: Low
  • 1: High
UART0/1 TX Encoding UART1 UART0

CTS

  • 0: Low
  • 1: High

RXD[2]

  • 0: Low
  • 1: High

RXD[1]

  • 0: Low
  • 1: High

RXD[0]

  • 0: Low
  • 1: High

RTS

  • 0: Low
  • 1: High

RXD[2]

  • 0: Low
  • 1: High

RXD[1]

  • 0: Low
  • 1: High

RXD[0]

  • 0: Low
  • 1: High
Table 26.  I2C/SMBus Bit Field Encoding in LTPI Frame
Name Bit Field Encoding
7 6 5 4 3 2 1 0
I2C/SM Bus 0/1 Encoding I2C/SMBus1 I2C/SMBus0
I2C/SMBus event as defined in the I2C/SMBus Event Bit Encoding table.
Table 27.  LTPI Default I/O Frame

Frame Offset

(bytes)

Size

(bits)

 Bit Field Description
7 6 5 4 3 2 1 0  
0 8 Comma Symbol Comma symbol as defined in the Frame Type and Frame Subtype table.
1 8 Frame Subtype Frame subtype as defined in the Frame Type and Frame Subtype table.
2 8 Frame Counter Frame counter used to decode NL GPIOs (refer to GPIO Channel appendix section).
3 8 Low Latency GPIO 0

LL GPIOs as defined in the LTPI GPIO Channel Encoding table.
4 8 Low Latency GPIO 1

LL GPIOs as defined in the LTPI GPIO Channel Encoding table.
5 8 Normal Latency GPIO 0

NL GPIOs as defined in the LTPI GPIO Channel Encoding table.
6 8 Normal Latency GPIO 1

NL GPIOs as defined in the LTPI GPIO Channel Encoding table.
7 8 UART0 and UART1 UART0 and UART1 as defined in the UART Channel Encoding table.
8 8 I2C/SMBus0 and I2C/SMBus1 I2C/SMBus0 and I2C/SMBus1 as defined in the I2C/SMBus Bit Field Encoding in LTPI Frame table.
9 8 I2C/SMBus2 and I2C/SMBus3 I2C/SMBus2 and I2C/SMBus3 as defined in the I2C/SMBus Bit Field Encoding in LTPI Frame table.
10 8 I2C/SMBus4 and I2C/SMBus5 I2C/SMBus4 and I2C/SMBus5 as defined in the I2C/SMBus Bit Field Encoding in LTPI Frame table.
11 8 OEM Reserved OEM reserved
12 8
13 8
14 8
15 8 CRC CRC8 checksum
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