LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
3.4.2. Simulation Output
The figure below shows the results after the completion of a successful design example simulation using the QuestaSim* simulator.
Figure 24. Read/Write Transaction from I2C Channel through I/O FrameShows the read/write transaction from the I2C channel carries over time through the I/O frame.
Figure 25. Read/Write Transaction from Data Channel through Data FrameShows the read/write transaction from the data channel carries over time through the data frame.
Figure 26. Read/Write Transaction from GPIO Channel through I/O FrameShows the read/write transaction from the GPIO channel carries over time through the I/O frame.
Figure 27. Simulation Waveform—LTPI Channel ControllerShows the waveform at the controller after the completion of a successful example design simulation using the ModelSim* simulator. Refer to the Signal Description section for more details on signal.
Figure 28. Simulation Waveform—LTPI Channel TargetShows the waveform at the target after the completion of a successful design example simulation using the ModelSim* simulator. Refer to the Signal Description section for more details on signal.
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