LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 844310
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Pro Edition Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters

On the IP Configuration tab, specify the parameters for your IP core variation. Refer to the following tables for more information about the specific LVDS Tunneling Protocol and Interface (LTPI) IP parameters.

Figure 16.  LVDS Tunneling Protocol and Interface (LTPI) IP Parameters—General Tab
Table 38.   LVDS Tunneling Protocol and Interface (LTPI) IP Parameter Description—General Tab
Parameter Range Selection Default Setting Description
Device Type
  • Controller
  • Target
 Controller Specify if the IP is used as SCM or HPM.
LTPI Major Version 0–15 1

Indicates the major LTPI version number.

This option is greyed out and always set to 1.
LTPI Minor Version 0–15 0

Indicates the minor LTPI version number.

This option is greyed out and always set to 0.
Interface Channels
Enable NL/LL GPIO Channel On/Off On Enables or disables low latency (LL) and normal latency (NL) GPIO channel.
Enable I2C SMbus Channel On/Off On Enables or disables the I2C/SMBus channel.
Enable UART Channel On/Off On Enables or disables the UART channel.
Enable Data Channel On/Off On Enables or disables the data channel.
Enable OEM Channel On/Off On Enables or disables the OEM channel.
CSR Lite On/Off Off Enables or disables the reduced number of CSR registers.
Enable Status Interface On/Off Off Enables or disables the status signals.
Enable Error Interface On/Off Off Enables or disables the error signals
Figure 17.  LVDS Tunneling Protocol and Interface (LTPI) IP Parameters—Channel Setting Tab
Table 39.   LVDS Tunneling Protocol and Interface (LTPI) IP Parameter Description—Channel Setting Tab
Parameter Range Selection Default Setting Description
Number of NL GPIO Interface 1–1024 16 Specifies the number of NL GPIO.
Number of I2C Bus Interface 1–6 6 Specifies the number of the I2C bus interface.
I2C Bus Speed Mode
  • STANDARD(100 KHz)
  • FAST(400 KHz)
 STANDARD(100 KHz) Selects the I2C bus speed.
Number of UART Bus Interface
  • 1
  • 2
 2 Specifies the number of the UART buses.
UART BAUD Rate
  • 9600
  • 115200
 9600 Sets the baud rate for the UART channels.
Data Channel Mailbox Enable
  • 0
  • 1
 1 Enables the data channel mailbox.
OEM Data Width 1–32 32 Specifies the OEM data width.
Figure 18.  LVDS Tunneling Protocol and Interface (LTPI) IP Parameters—Link Configuration Tab
Table 40.   LVDS Tunneling Protocol and Interface (LTPI) IP Parameter Description—Link Configuration Tab
Parameter Range Selection Default Setting Description
Select Link Mode
  • SDR
  • DDR
 SDR Selects the link mode supported by the DDR capability.
Link Speed Capability
  • X1 (25 MHz)
  • X2 (50 MHz)
  • X3 (75 MHz)
  • X4 (100 MHz)
  • X6 (150 MHz)
  • X8 (200 MHz)
  • X10 (250 MHz)
 X1 (25 MHz) Specifies the clock supported by LVDS.
Select System Clock
  • 60
  • 100
 60 Selects the system clock.
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