LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals
These signals are only applicable for the LTPI controller if the data channel is enabled.
The Avalon® memory-mapped interface signals are on the system_clk domain.
Signal Name | Direction | Size | Description |
---|---|---|---|
avmm_slv_write | Input | 1 | Indicates a write transfer. If present, write data is required. |
avmm_slv_read | Input | 1 | Indicates a read transfer. If present, read data is required. |
avmm_slv_address | Input | 32 | Write/read transfer address |
avmm_slv_writedata | Input | 32 | Write transfer data |
avmm_slv_byteenable | Input | 4 | Write/read byte enables |
avmm_slv_readdatavalid | Output | 1 | Valid to read data |
avmm_slv_readdata | Output | 32 | Read transfer data |
avmm_slv_waitrequest | Output | 1 | Wait request is asserted when unable to respond to read. |