LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 844310
Date 8/15/2025
Public
Document Table of Contents

1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals

These signals are only applicable for the LTPI controller if the data channel is enabled.

The Avalon® memory-mapped interface signals are on the system_clk domain.

Table 35.   Avalon® Memory-Mapped Secondary Interface Signals
Signal Name Direction Size Description
avmm_slv_write Input 1 Indicates a write transfer. If present, write data is required.
avmm_slv_read Input 1 Indicates a read transfer. If present, read data is required.
avmm_slv_address Input 32 Write/read transfer address
avmm_slv_writedata Input 32 Write transfer data
avmm_slv_byteenable Input 4 Write/read byte enables
avmm_slv_readdatavalid Output 1 Valid to read data
avmm_slv_readdata Output 32 Read transfer data
avmm_slv_waitrequest Output 1 Wait request is asserted when unable to respond to read.