LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 844310
Date 8/15/2025
Public
Document Table of Contents

3.4.1. Simulation Testbench Flow

The testbench executes the following activities for the LVDS Tunneling Protocol and Interface (LTPI) IP:
  1. Assert the global active low reset to reset the LVDS Tunneling Protocol and Interface (LTPI) IP.
  2. Deassert the global reset.
  3. Wait for pll_locked to be locked.
  4. Assert the link-aligned signal high with a 25 MHz refclk generated internally using a PLL.
  5. Switch the link speed to a preconfigured speed. By default, the link speed is 100 MHz in DDR mode.
  6. Monitor the local_link_state signal to ensure link state is transition to the operational state.
  7. Begin writing data to various interfaces such as LL/NL GPIO, UART, I2C, data, and OEM.
  8. Compare the data result sent via UART, OEM, and LL/NL GPIO at the receiving side. For I2C and data channel, compare the response at the sender side.