LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
3.4.1. Simulation Testbench Flow
The testbench executes the following activities for the LVDS Tunneling Protocol and Interface (LTPI) IP:
- Assert the global active low reset to reset the LVDS Tunneling Protocol and Interface (LTPI) IP.
- Deassert the global reset.
- Wait for pll_locked to be locked.
- Assert the link-aligned signal high with a 25 MHz refclk generated internally using a PLL.
- Switch the link speed to a preconfigured speed. By default, the link speed is 100 MHz in DDR mode.
- Monitor the local_link_state signal to ensure link state is transition to the operational state.
- Begin writing data to various interfaces such as LL/NL GPIO, UART, I2C, data, and OEM.
- Compare the data result sent via UART, OEM, and LL/NL GPIO at the receiving side. For I2C and data channel, compare the response at the sender side.