LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 844310
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Pro Edition Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1.4.4.10. Default Data Frame

The default data frame is in the LTPI operational mode to tunnel the LTPI data channel.

It is considered a random-access frame and it is only sent on demand when the data read or write access is triggered. The data frame supports only low latency GPIOs and data channel.

The supported memory access operations with LTPI tunneling are 1–4 byte writes and 1–4 byte reads. The following parameters are associated with the read and write requests:
  • Command—Identifies the memory operation.
  • Address—Address of read or write operation.
  • Data—1 to 4 bytes of data.
  • BE—Byte enable mask indicates number of bytes (1 to 4).

The following tables show the encoding of the data channel commands and the memory read write transaction, which uses the data channel in the LTPI interface.

Table 28.  Data Bus Command Encoding
Command Parameter Description Encoding Event [8b]
Read Request Address Indicates a request to read data from specific address. Byte enable mask indicates the number of bytes to read (1–4). 0h00
Write Request Address Data Indicates a request to write data from specific address. Byte enable mask indicates the number of bytes to write (1–4). 0h01
Read Completion Address Data Indicates a request to read operation is completed. Byte enable mask indicates the number of bytes valid in a read completion (1–4). 0h02
Write Completion Address Indicates a write operation result. 0h03
CRC Error N/A Indicates a data frame is received with CRC error and operation cannot be completed. 0h04
Reserved Reserved Reserved for future use. 0h03–0hFF
Table 29.  Memory Read and Write Operation Encoding
Name Bit Field Encoding
7 6 5 4 3 2 1 0
Memory Read Command = 0h00
Address Byte 3
Address Byte 2
Address Byte 1
Address Byte 0
Reserved Byte Enable
Reserved Byte 3 Byte 2 Byte 1 Byte 0
Memory Read Completion Command = 0h02
Address Byte 3
Address Byte 2
Address Byte 1
Address Byte 0
Read Operation Status Byte Enable
  • 0h: Success
  • 1h: Invalid Access
  • 1h–Fh: Reserved
 Byte 3 Byte 2 Byte 1 Byte 0
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
Memory Write Command = 0h01
Address Byte 3
Address Byte 2
Address Byte 1
Address Byte 0
Byte Enable
Reserved Reserved Reserved Reserved Byte 3 Byte 2 Byte 1 Byte 0
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
Memory Write Completion Command = 0h03
Address Byte 3
Address Byte 2
Address Byte 1
Address Byte 0
Write Operation Status Reserved
  • 0h: Success
  • 1h: Invalid Access
  • 1h–Fh: Reserved
 Reserved
Table 30.  LTPI Default Data Frame

Frame Offset

(bytes)

Size

(bits)

 Bit Field Description
7 6 5 4 3 2 1 0  
0 8 Comma Symbol Comma symbol as defined in the Speed Capabilities Encoding table.
1 8 Frame Subtype Frame subtype as defined in the Speed Capabilities Encoding table.
2 8 Low Latency GPIO 0

Low latency GPIOs as defined in the LTPI GPIO Channel Encoding table.
3 8 Low Latency GPIO 1

Low latency GPIOs as defined in the LTPI GPIO Channel Encoding table.
4 8 Tag Tag field that can be used by the user of the data channel (e.g., other CPLD or FPGA logic, BMC firmware, and others) to identify responses if multiple outstanding data requests are sent to LTPI.
5 8 Data Channel Payload Data channel payload as defined in the Memory Read and Write Operation Encoding table.
6 8
7 8
8 8
9 8
10 8
11 8
12 8
13 8
14 8
15 8 CRC CRC8 checksum
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