LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
1.4.1. Interface Tunneling Principle
The LTPI uses the following generic methods to capture and tunnel various LTPI channels:
- Sampling—The I/O states are sampled by LTPI and the samples are tunneled in the LTPI frames.
- Event/State detection—The set of events or states are identified for the channel and sent in LTPI frames based on the interface state.
- Random access read/writes requests—Random access memory mapped channel is triggered by external interface.
During operational state, channel interface supported by the LTPI IP can be categorize based on whether the RX and TX directions need to be synchronized for tunneling:
- Asynchronous—For a given channel and interface or link LTPI TX and RX paths are independent.
- Synchronous—For a given channel and interface or link LTPI TX and RX paths need to be synchronized to allow interface to work correctly after tunneling.
Channel | Capture Method | TX and RX Synchronization | Channel Characteristics |
---|---|---|---|
GPIO | Sampling | Asynchronous |
|
UART |
|
||
I2C/SMBus | Event/State detection | Synchronous |
|
Data bus | Random access |
|