LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 844310
Date 8/15/2025
Public
Document Table of Contents

2.3. Generating HDL for Synthesis and Simulation

Perform these steps to generate HDL for synthesis and simulation.
Steps to generate HDL for Synthesis and Simulation
  1. Click Generate HDL. The Generate window appears as shown below.
    Figure 19. HDL Generation for Synthesis and Simulation
  2. Configure the Synthesis and Simulation option.
    You have an option to select the HDL design file for both Simulation and Synthesis. For simulation, you can also choose to generate the simulation script for supported simulators.
  3. Click Generate to complete the IP generation process.