LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
1.1.8. IP Performance and Resource Utilization
The LVDS Tunneling Protocol and Interface (LTPI) IP resource utilization values are obtained from the Quartus® Prime Pro Edition software version 25.1.1.
LVDS Tunneling Protocol and Interface (LTPI) IP Configuration Setting | Combination ALUTs | Dedicated Logic Registers | Block Memory Bits | |
---|---|---|---|---|
Fixed Configuration | Variable Configuration | |||
|
|
5,961 | 5,674 | 3,584 |
|
4,176 | 4,271 | 3,520 | |
|
5,889 | 5,368 | 3,408 | |
|
4,121 | 3,976 | 3,344 |