LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
3.3. Configuring the Design Example Parameters
You can generate the simulation and hardware design example based on a fixed parameter configuration, as listed in the table below.
Parameter Name | Value |
---|---|
SYSTEM_CLOCK | 100 MHz |
LINK_MODE | DDR |
CAPABILITY | X4 (100 MHz) |
NL_GPIO | 16 |
LL_GPIO | 16 |
I2C | 6 |
I2C_MODE | STANDARD (100 KHz) |
UART | 2 |
UART_BAUD | 115200 |
DATA_CHANNEL_MAILBOX_EN | 0 |
OEM_DATA_WIDTH | 32 |
You can find the Verilog design file containing the fixed parameter configuration in the following locations:
- <design_example_dir>/ltpi_controller/synth/ltpi_controller.v
- <design_example_dir> /ltpi_target/synth/ltpi_target.v
Parameter Name | Value |
---|---|
SYSTEM_CLOCK | 100 MHz |
LINK_MODE | DDR |
CAPABILITY | X4 (100 MHz) |
NL_GPIO | 16 |
LL_GPIO | 16 |
I2C | 6 |
I2C_MODE | STANDARD (100 KHz) |
UART | 1 |
UART_BAUD | 115200 |
DATA_CHANNEL_MAILBOX_EN | 0 |
OEM_DATA_WIDTH | 32 |