LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
844310
Date
8/15/2025
Public
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
1.4.6.3. Operational Mode
Operational mode is the primary state for most of the LTPI link, during which the SCM and HPM continuously exchange I/O frames in both directions.
Figure 12. LTPI Operational State with I/O Frames Stream
When a data channel frame is generated, it interleaves the I/O frame traffic as shown in the following figure.
Figure 13. LTPI Operational State with Data Frames Interleaving I/O Frames Stream
The operational state remains infinite between SCM and HPM until the following conditions occur:
No. | Condition | Switch State |
---|---|---|
1 | Soft reset active high | Switch to advertise state |
2 | Hard reset active high (CPLD/FPGA reset or power lost) |
Switch to link detect state |
3 | Signal lost after 7 consecutive frames are lost in the operational state. | Switch to link detect state |
The following figure illustrates an end-to-end flow from the link reset to the link operational example.
Figure 14. Link Training and Configuration Flow