LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 844310
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Pro Edition Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

6.2. I2C Channel

The I2C/SMBus channel tunnels I2C/SMBus buses through the LTPI interface where the controller can be located on either the SCM or HPM.

The main use case is shown in the following figure, where the BMC on SCM controls the I2C/SMBus links with the target devices on HPM.

Figure 32. I2C Mapping in LTPI I2C Channel

I2C/SMBus SCL and SDA signals are bidirectional and can be driven by either the controller or target devices during transactions. Therefore, they cannot be tunneled directly through LTPI like GPIO or UART signals. Instead, LTPI uses an event-based model for I2C/SMBus channels. Events and states are captured on one side and recovered on the other. When the controller generates an event (like a START condition), the local SCL line is held until the remote event is received and processed. Once processed, the SCL line is released. The I2C/SMBus relays in the LTPI manage the states of the SCL and SDA signals.

To handle LTPI latency and turnaround time, the clock stretching method from the I2C/SMBus specification is used. Refer to the following figure for the state transition that follows the behavior and event exchange flows between the controller and the target.

Figure 33. State Transition

The received events do not need to be confirmed with an echo message, except for the data received events. An echo is sent for these events to differentiate between subsequent incoming data events within a byte transmission. For example:

  1. New data event is started by one end and is sent continuously on LTPI.
  2. When a data bit is received by the other end, it starts sending data echo continuously to confirm the reception of the data event.
  3. When a data bit is regenerated on the physical bus, a data received event starts sending continuously to confirm regeneration. The other end is still sending data event, which should be ignored until the data received event echo is received as a differentiator between the subsequent data events.
  4. When the data received event is received by the other end, the data received echo is transmitted continuously until a new data event is generated.

The I2C/SMBus events are defined with binary encoding in the following table. By using 4-bit encoding, an 8-bit LTPI frame field can accommodate two I2C/SMBus interfaces.

Table 50.  I2C/SMBus Event Bit Encoding
Bus Event Direction Description Encoding Event [4b]
Idle Bidirectional I2C/SMBus LTPI relay is in idle state. 0b0000
Start Controller to target Start Event detected on Controller side. 0b0001
Start Received Target to controller Start event recovered on the target side. 0b0010
Stop Controller to target Stop Event detected on Controller side. 0b0011
Stop Received Target to controller Stop event recovered on the target side. 0b0100
Data Received Bidirectional SDA bit value recovered on remote side. 0b0101
Data 0 Bidirectional Send SDA bit value 0. 0b0110
Data 1 Bidirectional Send SDA bit value 1. 0b0111
Start Echo Target to controller Event used to indicate that the start event is correctly received by the target side. If the echo is not received within expected time, i.e., frame turnaround time (typically 1–2 LTPI frames), the event can be repeated immediately without waiting for the start event timeout. 0b1000
Stop Echo Controller to target Optional stop event correctly received by target side. If the echo is not received within expected time, i.e., frame turnaround time (typically 1–2 LTPI frames), the event can be repeated immediately without waiting for the start event timeout. 0b1001
Data 0 Echo Bidirectional Send SDA bit value 0 received correctly. If the echo is not received within expected time, i.e., frame turnaround time (typically 1–2 LTPI frames), the event can be repeated immediately without waiting for the start event timeout. 0b1010
Data 1 Echo Bidirectional Send SDA bit value 1 received correctly. If the echo is not received within expected time, i.e., frame turnaround time (typically 1–2 LTPI frames), the event can be repeated immediately without waiting for the start event timeout. 0b1011
Data Received Echo Bidirectional Event used to indicate that the data received event was correctly received. It is used to differentiate between consecutive data 0/1 events during byte transmission. 0b1100
Reserved Reserved Reserved for future use. 0b1101–0b1111
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