HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

5.2.5. RX PHY Address Map

The transceiver component is word addressed.

Address Name Description
0x0000 RX Core Status Control Refer Table 24 below
0x0001 PHY Status Control Refer Table 25 below
0x0002 PLL Status Refer Table 26 below
0x0003 NIOS Control Refer Table 27 below
0x0004 TMDS Status Refer Table 28 below
Table 24.   RX Core Status Control (0x0000)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
RX Core Locked 0 RO Indicates RX Core has achieved alignment lock 0x0
Table 25.   PHY Status Control (0x0001)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
RX PHY Ready 0 RO Indicates RX PHY is ready 0x0
Table 26.   PLL Status (0x0002)
Name Bit Access Description Reset
Reserved 31:2 RO — 0x0
IOPLL FRL Clock Locked 1 RO Indicates FRL Clock IOPLL archived locked 0x0
IOPLL TMDS Clock Locked 0 RO Indicates TMDS Clock IOPLL archived locked 0x0
Table 27.   NIOS Control (0x0003)
Name Bit Access Description Reset
Reserved 31:1 WO — 0x0
EDID RAM Access 0 WO Indicates Read or Write on the EDID RAM is in progress 0x0
Table 28.   TMDS Status (0x0004)
Name Bit Access Description Reset
Reserved 31:25 RO — 0x0
TMDS Measure Valid 24 RO Indicates validity of Measure value 0x0
TMDS Measure Frequency 23:0 RO Measurement of RX TMDS clock —
Level Two Title