The HDMI TX PHY performs the following main functions:
- Allows software to switch the transceiver reference clock from the fr_clk to the tx_tmds_clk. TX PHY includes a free running fr_clk as reference clock 0 to handle the specific HDMI use case where there is no refclk to the transceiver due to the HDMI cable not plugged in (refclk to the transceiver is coming from the HDMI RX connector). Without refclk transceiver input, power-up calibration takes longer to complete.
- Allows software to reconfigure the TX transceivers according to the video pixel rate to be transmitted.
- Generates video clock (vid_clk) and link-speed clock (ls_clk) from tx_tmds_clk.
- Ingests parallel HDMI RX data and outputs serial HDMI data.
Software accesses the transceiver reconfiguration registers via the av_mm_control bus and the Avalon Bridge, which directs accesses for the corresponding address range to the transceiver reconfiguration registers. The Avalon Mux must be setup accordingly via the RX_RCFG_EN bit. Refer to the TX PHY Address Map section for HDMI 2.0.
Various other registers are provided for the software (refer to the TX PHY Address Map section for HDMI 2.0). These provide various statuses and controls, and some debug information to the controlling software.
The IOPLL takes the rx_tmds_clk and generates a reference clock for the RX transceiver’s CMU or CDR PLL as well as vid_clk and ls_clk which are connected to the HDMI RX core.
Oversampling operates on the TX side in case the data received is below the 1 Gbps minimum transceiver data rate. Depending on the frequency band this oversampling could be a factor of 3, 4 or 5.
The frequency of ls_clk is the TMDS data rate per lane per 20. Note that when oversampling is active, the transceiver data rate is three, four or five times higher than the TMDS data rate.
The vid_clk frequency depends also on the color depth:
vid_clk frequency = ls_clk / color depth ratio
|Bits per Color||Color Depth Ratio|