HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Public
Document Table of Contents

6.2.5. TX PHY Address Map

The transceiver component is word addressed.
Address Name Description
0x0000 Reconfig Status Control Refer Table 44 below
0x0001 PHY Status Control Refer Table 45 below
0x0002 PLL Status Refer Table 46 below
0x0003 NIOS Control Refer Table 47 below
0x0004 TMDS Status Refer Table 48 below
Table 44.  RX Core Status Control (0x0000)
Name Bit Access Description Reset
Reserved 31:1 RO 0x0
TX Reconfig Done 0 RO Indicates TX PHY reconfiguration is complete 0x0
Table 45.  PHY Status Control (0x0001)
Name Bit Access Description Reset
Reserved 31:1 RO 0x0
TX PHY Ready 0 RO Indicates TX PHY is ready 0x0
Table 46.  PLL Status (0x0002)
Name Bit Access Description Reset
Reserved 31:2 RO 0x0
IOPLL FRL Clock Locked 1 RO Indicates FRL Clock IOPLL archived locked 0x0
TX PHY PLL Locked 0 RO Indicates TX PHY IOPLL archived locked 0x0
Table 47.  NIOS Control (0x0003)
Name Bit Access Description Reset
Reserved 31:1 WO 0x0
TX Init Done 0 WO Indicates software is ready 0x0
Table 48.  TMDS Status (0x0004)
Name Bit Access Description Reset
Reserved 31:25 RO 0x0
TMDS Measure Valid 24 RO Indicates validity of Measure value 0x0
TMDS Measure Frequency 23:0 RO Measurement of TX TMDS clock