HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents
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5.1.2. Dynamic Reconfiguration

The RX reconfiguration management is handled predominantly by the RTL.

The software is mainly used to switch the reference clock over from the fixed rate clock to the RX TMDS clock (via IOPLL). This is because the transceiver requires a clock to be present at power‑up.

The reconfiguration management block measures the frequency of the incoming TMDS clock. It then uses the color depth provided by the HDMI RX core to select PLL configurations from a look-up-table. The PLL registers are then reprogrammed with these data and reset.

The TMDS clock is monitored along so that standard changes can be detected. The HDMI RX core also indicates when an I2C access has occurred and informs the RX PHY for the same purpose (e.g. a change in UHD to HD video may result in a different data rate but the same TMDS clock).