HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Public
Document Table of Contents

7.1. PHY Arbiter IP Ports

Table 49.  PHY Arbiter IP Ports
Interface Port Type Clock Domain Port Direction Description
clk Clock clk Input Free-running system clock input (100 MHz)
reset Reset reset Input Main asynchronous reset
rxphy_rcfg_master Avalon memory-mapped clk rxphy_rcfg_master_write Output Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter
clk rxphy_rcfg_master_read Output

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY Arbiter.

Only valid when SEPARATE_RCFG_INTF_EN = 0
clk rxphy_rcfg_master_address [9:0] Output
clk rxphy_rcfg_master_writedata [31:0] Output
clk rxphy_rcfg_master_readdata [31:0] Input
clk rxphy_rcfg_master_waitrequest Input
rxphy_rcfg_slave Conduit clk rxphy_rcfg_slave_write [3:0] Input

4x Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter

rxphy_reconfig_en signals to PHY arbiter that that RX PHY requires access to transceivers

rxphy_cal_busy signals from each transceiver that a calibration is in progress

rxphy_reconfig_cal_busy signals back from PHY arbiter that transceiver is undergoing calibration or reconfiguration

rxphy_rcfg_slave_chan indicates which transceiver is to be accessed

Only valid when SEPARATE_RCFG_INTF_EN = 0

clk rxphy_rcfg_slave_read [3:0] Input
clk rxphy_rcfg_slave_address [39:0] Input
clk rxphy_rcfg_slave_writedata [127:0] Input
clk rxphy_rcfg_slave_readdata [127:0] Output
clk rxphy_rcfg_slave_waitrequest [3:0] Output
clk rxphy_reconfig_en Output
clk rxphy_cal_busy [3:0] Input
clk rxphy_reconfig_cal_busy [3:0] Intput
clk rxphy_rcfg_slave_chan [1:0] Output
rxphy_rcfg_slave_#(# values 3:0) Avalon memory-mapped clk rxphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter, one for each channel (indicated by #)

Only valid when SEPARATE_RCFG_INTF_EN = 1
clk rxphy_rcfg_slave_read_# Input
clk rxphy_rcfg_slave_address_# [9:0] Input
clk rxphy_rcfg_slave_writedata_# [31:0] Input
clk rxphy_rcfg_slave_readdata_# [31:0] Output
clk rxphy_rcfg_slave_waitrequest_# Output
rxphy_rcfg_slave_#(# values 3:0) Conduit clk rxphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter, one for each transceiver channel

rxphy_reconfig_en_# signals to PHY arbiter that RX PHY requires access to transceivers

rxphy_cal_busy_# signals from each transceiver that a calibration is in progress

rxphy_reconfig_cal_busy_# signals back from PHY Arbiter that transceiver is undergoing calibration or reconfiguration

Only valid when SEPARATE_RCFG_INTF_EN = 1

clk rxphy_rcfg_slave_read_# Input
clk rxphy_rcfg_slave_address_# [9:0] Input
clk rxphy_rcfg_slave_writedata_# [31:0] Input
clk rxphy_rcfg_slave_readdata_# [31:0] Output
clk rxphy_rcfg_slave_waitrequest_# Output
clk rxphy_reconfig_en_# Output
clk rxphy_cal_busy_# Output
clk rxphy_reconfig_cal_busy_# Output
txphy_rcfg_master Avalon memory-mapped clk txphy_rcfg_master_write Output

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter

Only valid when SEPARATE_RCFG_INTF_EN = 0
clk txphy_rcfg_master_read Output
clk txphy_rcfg_master_address [9:0] Output
clk txphy_rcfg_master_writedata [31:0] Output
clk txphy_rcfg_master_readdata [31:0] Input
clk txphy_rcfg_master_waitrequest Input
txphy_rcfg_slave Conduit clk txphy_rcfg_slave_write [3:0] Input

4x Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter

txphy_reconfig_en signals to PHY arbiter that TX PHY requires access to transceivers

txphy_cal_busy signals from each transceiver that a calibration is in progress

txphy_reconfig_cal_busy signals back from PHY Arbiter that transceiver is undergoing calibration or reconfiguration

txphy_rcfg_slave_chan indicates which transceiver is to be accessed

Only valid when SEPARATE_RCFG_INTF_EN = 0

clk txphy_rcfg_slave_read [3:0] Input
clk txphy_rcfg_slave_address [39:0] Input
clk txphy_rcfg_slave_writedata [127:0] Input
clk txphy_rcfg_slave_readdata [127:0] Output
clk txphy_rcfg_slave_waitrequest [3:0] Output
clk txphy_reconfig_en Output
clk txphy_cal_busy [3:0] Output
clk txphy_reconfig_cal_busy [3:0] Input
clk txphy_rcfg_slave_chan [1:0] Output
txphy_rcfg_master_#(# values 3:0) Avalon memory-mapped clk txphy_rcfg_master_write_# Output

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter, one for each channel (indicated by #)

Only valid when SEPARATE_RCFG_INTF_EN = 1
clk txphy_rcfg_master_read_# Output
clk txphy_rcfg_master_address_# [9:0] Output
clk txphy_rcfg_master_writedata_# [31:0] Output
clk txphy_rcfg_master_readdata_# [31:0] Input
clk txphy_rcfg_master_waitrequest_# Input
txphy_rcfg_slave_#(# values 3:0) Conduit clk txphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter. one for each transceiver channel

txphy_reconfig_en_# signals to PHY arbiter that TX PHY requires access to transceivers

txphy_cal_busy_# signals from each transceiver that a calibration is in progress

txphy_reconfig_cal_busy_# signals back from PHY Arbiter that transceiver is undergoing calibration or reconfiguration

Only valid when SEPARATE_RCFG_INTF_EN = 1

clk txphy_rcfg_slave_read_# Input
clk txphy_rcfg_slave_address_# [9:0] Input
clk txphy_rcfg_slave_writedata_# [31:0] Input
clk txphy_rcfg_slave_readdata_# [31:0] Output
clk txphy_rcfg_slave_waitrequest_# Output
clk txphy_reconfig_en_# Output
clk txphy_cal_busy_# Output
clk txphy_reconfig_cal_busy_# Input