HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
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7.1. PHY Arbiter IP Ports

Table 49.  PHY Arbiter IP Ports
Interface Port Type Clock Domain Port Direction Description
clk Clock — clk Input Free-running system clock input (100 MHz)
reset Reset — reset Input Main asynchronous reset
rxphy_rcfg_master Avalon memory-mapped clk rxphy_rcfg_master_write Output Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter
clk rxphy_rcfg_master_read Output

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY Arbiter.

Only valid when SEPARATE_RCFG_INTF_EN = 0
clk rxphy_rcfg_master_address [9:0] Output
clk rxphy_rcfg_master_writedata [31:0] Output
clk rxphy_rcfg_master_readdata [31:0] Input
clk rxphy_rcfg_master_waitrequest Input
rxphy_rcfg_slave Conduit clk rxphy_rcfg_slave_write [3:0] Input

4x Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter

rxphy_reconfig_en signals to PHY arbiter that that RX PHY requires access to transceivers

rxphy_cal_busy signals from each transceiver that a calibration is in progress

rxphy_reconfig_cal_busy signals back from PHY arbiter that transceiver is undergoing calibration or reconfiguration

rxphy_rcfg_slave_chan indicates which transceiver is to be accessed

Only valid when SEPARATE_RCFG_INTF_EN = 0
clk rxphy_rcfg_slave_read [3:0] Input
clk rxphy_rcfg_slave_address [39:0] Input
clk rxphy_rcfg_slave_writedata [127:0] Input
clk rxphy_rcfg_slave_readdata [127:0] Output
clk rxphy_rcfg_slave_waitrequest [3:0] Output
clk rxphy_reconfig_en Output
clk rxphy_cal_busy [3:0] Input
clk rxphy_reconfig_cal_busy [3:0] Intput
clk rxphy_rcfg_slave_chan [1:0] Output
rxphy_rcfg_slave_#(# values 3:0) Avalon memory-mapped clk rxphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter, one for each channel (indicated by #)

Only valid when SEPARATE_RCFG_INTF_EN = 1
clk rxphy_rcfg_slave_read_# Input
clk rxphy_rcfg_slave_address_# [9:0] Input
clk rxphy_rcfg_slave_writedata_# [31:0] Input
clk rxphy_rcfg_slave_readdata_# [31:0] Output
clk rxphy_rcfg_slave_waitrequest_# Output
rxphy_rcfg_slave_#(# values 3:0) Conduit clk rxphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter, one for each transceiver channel

rxphy_reconfig_en_# signals to PHY arbiter that RX PHY requires access to transceivers

rxphy_cal_busy_# signals from each transceiver that a calibration is in progress

rxphy_reconfig_cal_busy_# signals back from PHY Arbiter that transceiver is undergoing calibration or reconfiguration

Only valid when SEPARATE_RCFG_INTF_EN = 1

clk rxphy_rcfg_slave_read_# Input
clk rxphy_rcfg_slave_address_# [9:0] Input
clk rxphy_rcfg_slave_writedata_# [31:0] Input
clk rxphy_rcfg_slave_readdata_# [31:0] Output
clk rxphy_rcfg_slave_waitrequest_# Output
clk rxphy_reconfig_en_# Output
clk rxphy_cal_busy_# Output
clk rxphy_reconfig_cal_busy_# Output
txphy_rcfg_master Avalon memory-mapped clk txphy_rcfg_master_write Output

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter

Only valid when SEPARATE_RCFG_INTF_EN = 0
clk txphy_rcfg_master_read Output
clk txphy_rcfg_master_address [9:0] Output
clk txphy_rcfg_master_writedata [31:0] Output
clk txphy_rcfg_master_readdata [31:0] Input
clk txphy_rcfg_master_waitrequest Input
txphy_rcfg_slave Conduit clk txphy_rcfg_slave_write [3:0] Input

4x Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter

txphy_reconfig_en signals to PHY arbiter that TX PHY requires access to transceivers

txphy_cal_busy signals from each transceiver that a calibration is in progress

txphy_reconfig_cal_busy signals back from PHY Arbiter that transceiver is undergoing calibration or reconfiguration

txphy_rcfg_slave_chan indicates which transceiver is to be accessed

Only valid when SEPARATE_RCFG_INTF_EN = 0
clk txphy_rcfg_slave_read [3:0] Input
clk txphy_rcfg_slave_address [39:0] Input
clk txphy_rcfg_slave_writedata [127:0] Input
clk txphy_rcfg_slave_readdata [127:0] Output
clk txphy_rcfg_slave_waitrequest [3:0] Output
clk txphy_reconfig_en Output
clk txphy_cal_busy [3:0] Output
clk txphy_reconfig_cal_busy [3:0] Input
clk txphy_rcfg_slave_chan [1:0] Output
txphy_rcfg_master_#(# values 3:0) Avalon memory-mapped clk txphy_rcfg_master_write_# Output

Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter, one for each channel (indicated by #)

Only valid when SEPARATE_RCFG_INTF_EN = 1
clk txphy_rcfg_master_read_# Output
clk txphy_rcfg_master_address_# [9:0] Output
clk txphy_rcfg_master_writedata_# [31:0] Output
clk txphy_rcfg_master_readdata_# [31:0] Input
clk txphy_rcfg_master_waitrequest_# Input
txphy_rcfg_slave_#(# values 3:0) Conduit clk txphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY arbiter. one for each transceiver channel

txphy_reconfig_en_# signals to PHY arbiter that TX PHY requires access to transceivers

txphy_cal_busy_# signals from each transceiver that a calibration is in progress

txphy_reconfig_cal_busy_# signals back from PHY Arbiter that transceiver is undergoing calibration or reconfiguration

Only valid when SEPARATE_RCFG_INTF_EN = 1

clk txphy_rcfg_slave_read_# Input
clk txphy_rcfg_slave_address_# [9:0] Input
clk txphy_rcfg_slave_writedata_# [31:0] Input
clk txphy_rcfg_slave_readdata_# [31:0] Output
clk txphy_rcfg_slave_waitrequest_# Output
clk txphy_reconfig_en_# Output
clk txphy_cal_busy_# Output
clk txphy_reconfig_cal_busy_# Input
Level Two Title