HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents

5.2.2. Dynamic Reconfiguration

The RX reconfiguration management is handled predominantly by the RTL.

The software is mainly used to read the FRL Rate set by the source. If the rate is 0, the design will run in TMDS mode. If the rate is between 1 to 6, the design will run in FRL Mode.

For FRL mode, the Dynamic Reconfiguration profile ID is selected based on the FRL Rate value. For TMDS mode, the reconfiguration management block measures the frequency of the incoming TMDS clock. It then uses the color depth information provided by the HDMI RX core and selects the Dynamic Reconfiguration profile ID.

This profile ID represents the data rate to be configured on the RX PHY. The Dynamic Reconfiguration IP is then reprogrammed with these data and reset.