HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents
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6.2.1. Architecture

The HDMI TX PHY performs the following main functions:
  • Allows software to switch the transceiver reference clock from the tx_phy_refclk_frl to the tx_phy_refclk_tmds.
  • Allows software to reconfigure the TX transceivers according to the FRL rate or video pixel rate to be transmitted.
  • Generates video clock (vid_clk) and link-speed clock (tx_phy_clk).
  • Ingests parallel HDMI RX data and output serial HDMI data.

Software accesses the transceiver reconfiguration registers via the av_mm_control bus and the Avalon Bridge, which directs accesses for the corresponding address range to the transceiver reconfiguration registers. Various other registers are provided for the software (refer to TX PHY Address Map section. These provide various statuses and controls, and some debug information to the controlling software.

The IOPLL takes the tx_phy_clk and generates a frl_clk which are connected to the HDMI TX core.

Oversampling operates on the TX side in case the data received is below the 1 Gbps minimum transceiver data rat. Depending on the frequency band, this oversampling could be a factor of 2 or 8.

The frequency of tx_phy_clk is the TMDS data rate per lane per 80. Note that when oversampling is active, the transceiver data rate is 2 or 8 times higher than the TMDS data rate.

The vid_clk frequency is fixed to 225 MHz.