HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

6.1.5. TX PHY Address Map

Byte Address Name Description
0x0000 – 0x0FFF TX PMA Transceiver Avalon reconfiguration bus – accesses the transceiver channel set by PMA Channel
0x1000 - 0x1FFF fPLL Avalon reconfiguration bus for the fPLL
0x2000 - 0x27FF IOPLL Avalon reconfiguration bus for the IOPLL
0x2800 Power-up Cal Done Refer Table 32 below
0x2810 IOPLL Waitrequest Refer Table 33 below
0x2820 fPLL Waitrequest Refer Table 34 below
0x2830 TX PMA Cal Busy Refer Table 35 below
0x2840 PMA Channel Refer Table 36 below
0x2850 PMA Waitrequest Refer Table 37 below
0x2860 TX_RCFG_EN Refer Table 38 below
0x2870 TX_RST_PLL Refer Table 39 below
0x2880 TX_RST_XCVR Refer Table 40 below
0x2890 OS Refer Table 41 below
0x28F0 Config Refer Table 42 below
Table 32.  Power-up Cal Done (0x2800)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
Power-up Cal Done 0 RO 'High' indicates that power up calibration is complete 0x0
Table 33.  IOPLL Waitrequest (0x2810)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
IOPLL Waitrequest 0 RO Value of the waitrequest signal of the IOPLL’s reconfiguration Avalon bus. This can indicate a calibration in progress 0x0
Table 34.  fPLL Waitrequest (0x2820)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
fPLL Waitrequest 0 RO Value of the waitrequest signal of the fPLL’s reconfiguration Avalon bus. This can indicate a calibration in progress 0x0
Table 35.  TX PMA Cal Busy (0x2830)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
TX PMA Cal Busy 0 RO 'High' indicates TX PMA (transceiver) is in calibration 0x0
Table 36.  PMA Channel (0x2840)
Name Bit Access Description Reset
Reserved 31:2 RO — 0x0
PMA Channel 1:0 R/W Set 0-3 to access the corresponding transceiver channel 0x0
Table 37.  PMA Waitrequest (0x2850)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
PMA Waitrequest 0 RO Value of the waitrequest signal of the PMA’s (transceiver) reconfiguration Avalon bus. This can indicate a calibration in progress 0x0
Table 38.  TX_RCFG_EN (0x2860)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
TX_RCFG_EN 0 R/W TX reconfiguration enable – controls the avalon mux. Setting this bit allows the av_mm_control bus to access the transceiver reconfiguration registers 0x0
Table 39.  TX_RST_PLL (0x2870)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
TX_RST_PLL 0 R/W Resets the fPLL 0x0
Table 40.  TX_RST_XCVR (0x2880)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
TX_RST_XCVR 0 R/W Resets the transceiver’s TX, both analog and digital 0x0
Table 41.  OS (0x2890)
Name Bit Access Description Reset
Reserved 31:2 RO — 0x0
OS 1:0 R/W

Sets the oversampling ratio:

0x0 => 1

0x1 => 3

0x2 => 4

0x3 => 5 		0x0
Table 42.  Config (0x28F0)
Name Bit Access Description Reset
Reserved 31:2 RO — 0x0
SWAP_FPLL_FOR_ATXPLL 1 RO

‘0’ => fPLL is used to drive the TX transceiver

‘1’ => ATXPLL is used (not available yet) 		 
SWAP_IOPLL_FOR_FPLL 0 RO

‘0’ => IOPLL is used to produce ls_clk and vid_clk

‘1’ => fPLL is used (not available yet) 		0x0
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