HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents
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2. HDMI PHY Overview

The HDMI Intel® FPGA IP provides support for next generation video display interface technology.

The HDMI standard specifies a digital communications interface for use in both internal and external connections:

  • Internal connections—interface within a PC and monitor
  • External display connections—interface between a PC and monitor or projector, between a PC and TV, or between a device such a DVD player and TV display.

The HDMI system architecture consists of sinks and sources. A device may have one or more HDMI inputs and outputs.

The HDMI cable and connectors carry four differential pairs that make up the Transition Minimized Differential Signaling (TMDS) data and clock channels for HDMI 1.4 and HDMI 2.0. For HDMI 2.1, HDMI cable and connectors carry four fixed rate link (FRL) lanes of data. You can use these channels to carry video, audio, and auxiliary data.

The HDMI also carries a Video Electronics Standards Association (VESA) Display Data Channel (DDC) and Status and Control Data Channel (SCDC). The DDC configures and exchanges status between a single source and a single sink. The source uses the DDC to read the sink's Enhanced Extended Display Identification Data (E-EDID) to discover the sink's configuration and capabilities.

The optional Consumer Electronics Control (CEC) protocol provides high-level control functions between various audio-visual products in your environment.

The optional HDMI Ethernet and Audio Return Channel (HEAC) provides Ethernet compatible data networking between connected devices and an audio return channel in the opposite direction of TMDS. The HEAC also uses Hot-Plug Detect (HPD) line for link detection.

An HDMI interface consists of three color channels accompanied by a single clock channel. You can use each color line to transfer both individual RGB colors and auxiliary data.

The receiver uses the TMDS clock as a frequency reference for data recovery on the three TMDS data channels. This clock typically runs at the video pixel rate.

TMDS encoding is based on an 8-bit to 10-bit algorithm. This protocol attempts to minimize data channel transition, and yet maintain sufficient transition so that a sink device can lock reliably to the data stream.

There are three related PHY IP cores for HDMI:

  • PHY Arbiter Intel® FPGA IP

The TX and RX PHYs contain a simplex transceiver instantiation. The PHY Arbiter handles the arbitration between the RX or TX reconfiguration management access to the transceiver reconfiguration Avalon® memory-mapped interface to ensure fully dual-simplex operation – i.e., the instantiation of the transceivers of the RX and TX PHY can be merged, allowing transceivers to be fully utilized.

The PHYs and the Arbiter are designed to be used with the HDMI TX and RX core for easy creation of an HDMI TX and RX system for HDMI 2.0. and HDMI 21.1.

Figure 1. HDMI TX and RX Basic System

Each PHY contains an IOPLL to provide the ls_clk (link speed clock) and vid_clk to the corresponding core.

For Intel® Arria® 10 devices, the TX PHY block contains an fPLL to produce the high-speed clock for the transceiver TX. The high-speed serial clock for the RX side is produced by the CMU or CDR PLL within the transceiver RX.

For Intel® Agilex™ F-tile devices, the TX PHY and RX PHY reference clocks are generated by the System PLL clock IP.

The transceiver and PLLs must be dynamically reconfigured according to the video standard and data rate required. The RX and TX are reconfigured independently. Avalon® Bridges provide access from software to various registers within the PHY RTL as well as dynamic reconfiguration access to the PLLs and transceiver.

You must instantiate the HDMI core with Support FRL = 0 (for Intel® Arria® 10) or Support FRL = 1 (for Intel® Agilex™ F-tile) and Enable Active Video Protocol = AXIS-VVP Full to use Intel HDMI TX or RX PHY IP.