HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Public
Document Table of Contents

6.2.4. IP Configuration Parameters

Layout options allow the transceiver polarity to be swapped. This allows for flexibility in the PCB layout.
Table 43.  TX PHY Configuration Parameters
Parameter Value Description
Device family Agilex Targeted device family. This parameter inherits the value from the project device.
Supported HDMI Version 2.1 Currently only HDMI version 2.1 is supported.
Symbols per clock 4 symbols per clock Determines how many symbols are processed per clock.
Transceiver for Blue / Lane 0 0, 1, 2, 3 This parameter selects which transceiver channel carries the blue / TMDS 0 data. This allows any lane swaps on the circuit board to be corrected.
Transceiver for Green / Lane 1 0, 1, 2, 3 This parameter selects which transceiver channel carries the green / TMDS 1 data. This allows any lane swaps on the circuit board to be corrected.
Transceiverfor Red / Lane 2 0, 1, 2, 3 This parameter selects which transceiver channel carries the red / TMDS 2 data. This allows any lane swaps on the circuit board to be corrected.
Transceiver for Clock / Lane 3 0, 1, 2, 3 This parameter selects which transceiver channel carries the clock / TMDS 3 data. This allows any lane swaps on the circuit board to be corrected.
Figure 9. TX PHY Configuration Parameters