HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Public
Document Table of Contents

6.2.3. IP Ports

Interface Port Type Clock Domain Port Direction Description
reset Reset reset Input Main asynchronous reset
mgmt_clk Clock mgmt_clk Input Free-running system clock input (100 MHz)
tx_tmds_clk Clock tx_tmds_clk Input This clock frequency follows TMDS clock frequency. This clock is connected to the TMDS clock from the Intel HDMI RX IP
systempll_clk Clock systempll_clk Input Reference clock to RX Transceiver System PLL Clock (100 MHz). This clock is driven by F-tile Reference and System PLL clock IP output
tx_phy_refclk_frl Clock tx_phy_refclk_frl Input Reference clock to TX Transceiver for FRL (100 MHz). This clock is driven by F-tile Reference and System PLL clock IP output
tx_phy_refclk_tmds Clock tx_phy_refclk_tmds Input Reference clock to TX Transceiver for TMDS. Frequency depends on TMDS Clock frequency. This clock is driven by F-tile Reference and System PLL clock IP output
tx_vid_clk_in Clock tx_vid_clk_in Input Synchronous video clock
tx_serial_data Conduit tx_serial_data [3:0] Output HDMI serial TX data stream
tx_serial_data_n Conduit tx_serial_data_n [3:0] Output
txphy_rcfg_master Avalon memory-mapped mgmt_clk txphy_rcfg_master_write Output Avalon memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter
txphy_rcfg_master_read Output
txphy_rcfg_master_address [9:0] Output
txphy_rcfg_master_writedata [31:0] Output
txphy_rcfg_master_readdata [31:0] Input
txphy_rcfg_master_waitrequest Input
txphy_rcfg_master_readdatavalid Input
av_mm_control Avalon memory-mapped mgmt_clk av_mm_control_write Input Avalon memory-mapped interface for control of IP core
av_mm_control_read Input
av_mm_control_address [7:0] Input
av_mm_control_writedata [31:0] Input
av_mm_control_readdata [31:0] Output
phy_interface Conduit tx_phy_clk tx_parallel_data [319:0] Input TX parallel data. 80 Bits per transceiver
mgmt_clk sys_init Input Indicates reconfiguration management is ready
mgmt_clk device_ready Input Indicates readiness of device after power-up
mgmt_clk tx_tmds_freq [23:0] Input This clock frequency follows TMDS clock frequency
mgmt_clk tx_frl_rate [3:0] Input

0 = TMDS

1 = 3000 Mbps (3 lane)

2 = 6000 Mbps (3 lane)

3 = 6000 Mbps (4 lane)

4 = 8000 Mbps (4 lane)

5 = 10000 Mbps (4 lane)

6 = 12000 Mbps (4 lane)

mgmt_clk txphy_rcfg_curr_profile_id [14:0] Input Reconfiguration control registers
mgmt_clk txphy_rcfg_master_new_cfg_applied Input
mgmt_clk txphy_cal_busy_gated [3:0] Input
mgmt_clk txphy_rcfg_busy Output
mgmt_clk txphy_rcfg_master_new_cfg_applied_ack Output
mgmt_clk tx_os [1:0] Output

‘1’ => oversampling ratio of 2 (TMDS)

‘2’=> oversampling ratio of 8 (TMDS)

‘3’=> oversampling ratio of 2 (FRL)

frl_clk tx_pll_frl_locked Output Indicates FRL IOPLL is locked
tx_phy_clk tx_pll_locked [3:0] Output Indicates TX PHY IOPLL archived is locked
tx_phy_clk tx_phy_ready Output Indicates TX PHY is ready
tx_vid_clk Output Clock to Video data path on the Intel HDMI TX IP
tx_phy_clk Output Clock out recovered from the TX transceiver
tx_frl_clk Output Clock to FRL path on the TX core. Refer to Section 5.5 FRL Clocking Scheme of HDMI Intel FPGA IP Core User Guide for more details
tx_phy_clk tx_core_in_lock Output Indicates TX PHY is ready