HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents

1. HDMI PHY Intel® FPGA IP Quick Reference

Updated for:
Intel® Quartus® Prime Design Suite 22.3
IP Version 1.0.1
The Intel FPGA High-Definition Multimedia Interface (HDMI) PHY IP provides support for next-generation video display interface technology. The HDMI PHY Intel® FPGA IP is part of the Intel® FPGA IP Library, which is distributed with the Intel® Quartus® Prime software.
Note: All information in this document refers to the Intel® Quartus® Prime Pro Edition software, unless stated otherwise.
Information Description
IP Information Core Features
  • Conforms to the High-Definition Multimedia Interface (HDMI) Specification versions 1.4, 2.0b (Arria 10) and 2.1 (Agilex)
  • Supports transmitter and receiver on a single device transceiver quad
  • Supports pixel frequency up to 600 MHz for HDMI 2.0
  • Supports FRL Rate 1 to 6 for HDMI 2.1
Typical Application
  • Interfaces within a PC and monitor.
  • External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display
Device Family Intel® Arria® 10 and Intel® Agilex™ F-tile
Design Tools
  • Intel® Quartus® Prime software for IP design instantiation and compilation.
  • Timing Analyzer in the Intel® Quartus® Prime software for timing analysis.
  • ModelSim* - Intel® FPGA Edition or ModelSim* - Intel® FPGA Starter Edition, NCSim, Riviera-PRO* , VCS* , VCS* MX, and Xcelium* Parallel software for design simulation
Note: The High-bandwidth Digital Content Protection (HDCP) feature is not included in the Intel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel at: https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html