HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents
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5.2.1. Architecture

The HDMI RX PHY performs the following main functions:
  • Allows RTL to switch the transceiver reference clock from the rx_phy_cdr_refclk_frl to the rx_phy_cdr_refclk_tmds.
  • Reconfig Management block measures frequency of the incoming HDMI TMDS clock (rx_tmds_clk) to determine the received video pixel rate.
  • Reconfigures the RX transceivers according to the received FRL rate or video pixel rate.
  • Generates FRL Clock (rx_frl_clk) and link-speed clock (rx_phy_clk).

Recover serial HDMI data and output parallel HDMI RX data.

HDMI RX PHY has various registers that are provided for the software (refer to the RX PHY Address Map section). These registers provide various statuses and controls, and some debug information to the controlling software.

The IOPLL takes the rx_phy_clk and generates a frl_clk which are connected to the HDMI RX core.

Oversampling operates on the RX side in case the data received is below the 1 Gbps minimum transceiver data rate. For example, a video resolution with TMDS Bit Rates of 742.5 Mbps should configure the transceiver to operate at five times its data rate, which is 3.7125 Gb/s. The oversampling factor on the RX is set to 5 for data rates less than 1Gbps.

The frequency of rx_phy_clk is the TMDS data rate per lane per 40. Note that when oversampling is active, the transceiver data rate is five times higher than the TMDS data rate.

The vid_clk frequency is fixed to 225 MHz.