HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
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5.1.5. RX PHY Address Map

The transceiver component is byte addressed. To easily handle these accesses from a word addressed system, the bridge simply divides the address offset by four (shifts right by two) for the address regions where these components reside. For example, to access address offset 0x100 of the RX PMA, the software must read or write address 4 * 0x100 = 0x0400.
Table 12.  RX PHY Address Map
Address Name Description
0x0000 – 0x0FFF RX PMA Transceiver Avalon reconfiguration bus – accesses the transceiver channel set by PMA Channel.
0x1000 Measure Refer Table 13 below
0x1010 Measure Valid Refer Table 14 below
0x1020 Power-up Cal Done Refer Table 15 below
0x1030 RX PMA Cal Busy Refer Table 16 below
0x1040 PMA Channel Refer Table 17 below
0x1050 RX_RCFG_EN Refer Table 18 below
0x1060 RX_RST_XCVR Refer Table 19 below
0x1070 PMA Waitrequest Refer Table 20 below
0x1080 Config Refer Table 21 below
Table 13.  Measure (0x1000)
Name Bit Access Description Reset
Reserved 31:0 RO Measurement of RX TMDS clock. 0x0
Table 14.  Measure Valid (0x1010)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
Mesaure Valid 0 RO Indicates validity of Measure value. 0x0
Table 15.  Power-up Cal Done (0x1020)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
Power-up Cal Done 0 RO Indicates that power up calibration is complete. 0x0
Table 16.  RX PMA Cal Busy (0x1030)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
RX PMA Cal Busy 0 RO A high on this signal indicates RX PMA (transceiver) is in calibration mode. 0x0
Table 17.  PMA Channel (0x1040)
Name Bit Access Description Reset
Reserved 31:2 RO — 0x0
PMA Channel 1:0 R/W Set 0-2 to access the corresponding transceiver channel. 0x0
Table 18.  RX_RCFG_EN (0x1050)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
RX_RCFG_EN 0 R/W RX reconfiguration enable – controls the Avalon mux. Setting this bit allows the av_mm_control bus to access the transceiver reconfiguration registers. 0x0
Table 19.  RX_RST_XCVR (0x1060)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
RX_RST_XCVR 0 R/W Resets the transceiver’s RX, both analog and digital. 0x0
Table 20.  PMA Waitrequest (0x1070)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
PMA Waitrequest 0 RO Value of the waitrequest signal of the PMA’s (transceiver) reconfiguration Avalon bus. This can indicate a calibration in progress. 0x0
Table 21.  Config (0x1080)
Name Bit Access Description Reset
Reserved 31:1 RO — 0x0
SWAP_IOPLL_FOR_FPLL 0 RO

‘0’ => IOPLL is used to produce ls_clk and vid_clk

‘1’ => fPLL is used (not available yet) 		0x0
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