HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Document Table of Contents
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6.1.2. Dynamic Reconfiguration

The TX reconfiguration management is handled by software.

The software performs the following functions:

  • Switches the reference clock of the fPLL over from the fixed rate clock to the TX TMDS clock. This is because the transceiver requires a clock to be present at power‑up.
  • Reconfigures and resets the IOPLL to produce the correct ls_clk and vid_clk from the tx_tmds_clk.
  • Reconfigures and resets the fPLL to produce the correct output serial rate.
  • Resets and recalibrates the transceiver.
  • Calculates the required oversample rate and sets the oversampling register to communicate the required oversampling to the HDMI TX core.