HDMI PHY Intel FPGA IP User Guide

ID 732147
Date 10/31/2022
Public
Document Table of Contents

2.4. Resource Utilization

The resource utilization data indicates typical expected performance for the HDMI Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition software.
Table 5.  HDMI Data Rate
Device Maximum Data Rate (Mbps)
2 Pixels per Clock

(Support FRL = 0)

8 Pixels per Clock

(Support FRL = 1)

Intel® Arria® 10 5,940

(Example: 4Kp60 8 bpc)

Not supported
Intel® Agilex™ F-tile Not supported 12,000

(Example: 8Kp30 12 bpc)

Table 6.  HDMI Intel FPGA IP Resource Utilization
Device IP ALMs Logic Registers Memory
Bits M20K
Intel® Arria® 10 RX PHY 1093 1126 2264 3
TX PHY 338 341 216 2
Arbiter 73 41 0 0
Intel® Agilex™ F-tile RX PHY 1348 2369 40960 4
TX PHY 1516 2898 262144 16
Arbiter 7 8 0 0
Table 7.  Recommended Speed Grades for Intel Devices
Device Lane Rate (Mbps) Interface Width (bits) Speed Grades
Intel® Arria® 10 6,000 20 -1, -2
Intel® Agilex™ F-tile 12,000 40 -1