1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
2.3. Using the Fault Injection Debugger and IP Core
The Fault Injection Debugger works together with the IP core. First, you instantiate the IP core in your design, compile, and download the resulting configuration file into your device. Then, you run the Fault Injection Debugger from within the Intel® Quartus® Prime software or from the command line to simulate soft errors.
- The Fault Injection Debugger allows you to operate fault injection experiments interactively or by batch commands, and allows you to specify the logical areas in your design for fault injections.
- The command-line interface is useful for running the debugger via a script.
The Fault Injection Debugger communicates with the IP core via the JTAG interface. The IP accepts commands from the JTAG interface and reports status back through the JTAG interface.
Note: The IP core is implemented in soft logic in your device; therefore, you must account for this logic usage in your design. One methodology is to characterize your design’s response to SEU in the lab and then omit the IP core from your final deployed design.
You use the IP core with the following IP cores:
- The Error Message Register Unloader IP core, which reads and stores data from the hardened error detection circuitry in Intel FPGA devices.
- (Optional) The Advanced SEU Detection Intel® FPGA IP core, which compares single-bit error locations to a sensitivity map during device operation to determine whether a soft error affects it.
Figure 8. Fault Injection Debugger Overview Block Diagram
Instantiating the IP Core
Defining Fault Injection Areas
Using the Fault Injection Debugger
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