1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
184.108.40.206. Hierarchy Tagging
The Intel® Quartus® Prime hierarchy tagging feature allows you to improve design-effective FIT rate by tagging only the critical logic for device operation.
You can also define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides. Other advantages of hierarchy tagging are:
- Increases system stability by avoiding disruptive recovery procedures for inconsequential errors.
- Allows diverse corrective action for different design logic.
The .smh file contains a mask for design sensitive bits in a compressed format. The Intel® Quartus® Prime software generates the sensitivity mask for the entire design. The Intel® Arria® 10, Cyclone® V, and Stratix® V device families support hierarchy tagging.
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