AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

ID 683869
Date 9/28/2021
Document Table of Contents Hierarchy Tagging

The Intel® Quartus® Prime hierarchy tagging feature allows you to improve design-effective FIT rate by tagging only the critical logic for device operation.

You can also define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides. Other advantages of hierarchy tagging are:

  • Increases system stability by avoiding disruptive recovery procedures for inconsequential errors.
  • Allows diverse corrective action for different design logic.

The .smh file contains a mask for design sensitive bits in a compressed format. The Intel® Quartus® Prime software generates the sensitivity mask for the entire design. The Intel® Arria® 10, Cyclone® V, and Stratix® V device families support hierarchy tagging.

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