AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

ID 683869
Date 9/28/2021
Document Table of Contents

1.4. Internal Scrubbing

Intel® Arria® 10, select Cyclone® V (including SoC devices), and Stratix® V FPGAs support automatic CRAM error correction without reloading the original CRAM contents from an external copy of the original .sof.

The internal scrubbing feature corrects single-bit and double-adjacent errors automatically.

If the FPGA finds a CRC error in a CRAM frame, the FPGA reconstructs the frame from the error correcting code calculated for that frame. Then the FPGA writes the correct frame into the CRAM.

If you enable internal scrubbing, you must still plan a recovery sequence. Although scrubbing can restore the CRAM array to intended configuration, latency occurs between the soft error detection and correction. During this latency period, the FPGA may operate with errors. If the FPGA must scan a large number of configuration bits, this latency can be up to 100 milliseconds. For more information about latency refer to the device datasheet.

To enable internal scrubbing, click Assignments > Device > Device and Pin Options > Error Detection CRC and turn on the Enable internal scrubbing option.