AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

ID 683869
Date 9/28/2021
Document Table of Contents

1.9. CRAM Error Detection Settings Reference

To define these settings in the Intel® Quartus® Prime software, point to Assignments > Device > Device and Pin Options > Error Detection CRC.
Figure 7.  Device and Pin Options Error Detection CRC Tab

Table 1.  CRC Errors Settings
Setting Description
Enable Error Detection CRC_ERROR pin Enables CRAM frame scanning
Enable open drain on CRC_ERROR pin Enables the CRC_ERROR pin as an open-drain output
Divide error check frequency by To guarantee the availability of a clock, the EDCRC function operates on an independent clock generated internally on the FPGA itself. To enable EDCRC operation on a divided version of the clock, select a value from the list.