AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

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ID 683869
Date 9/28/2021
Public
Document Table of Contents
Document Table of Contents x
1. Mitigating Single Event Upset 2. Debugging Single Event Upset Using the Fault Injection Debugger
1. Mitigating Single Event Upset x
1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
1.2. Mitigating SEU Effects in Embedded User RAM x
1.2.1. Configuring RAM to Enable ECC
1.5. SEU Recovery x
1.5.1. Planning for SEU Recovery 1.5.2. Designating the Sensitivity of the Design Hierarchy 1.5.3. Advanced SEU Detection IP Core
1.5.2. Designating the Sensitivity of the Design Hierarchy x
1.5.2.1. Hierarchy Tagging 1.5.2.2. Using Partitions to Specify Logic Sensitivity ID
1.5.3. Advanced SEU Detection IP Core x
1.5.3.1. On-Chip Sensitivity Processor 1.5.3.2. External Sensitivity Processor
1.6. Intel® Quartus® Prime Software SEU FIT Reports x
1.6.1. SEU FIT Parameters Report 1.6.2. Projected SEU FIT by Component Usage Report 1.6.3. Enabling the Projected SEU FIT by Component Usage Report
1.6.2. Projected SEU FIT by Component Usage Report x
1.6.2.1. Component FIT Rates 1.6.2.2. Raw FIT 1.6.2.3. Utilized FIT 1.6.2.4. Mitigated FIT 1.6.2.5. Architectural Vulnerability Factor
1.6.2.3. Utilized FIT x
1.6.2.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 1.6.2.3.2. Considerations for Small Designs
2. Debugging Single Event Upset Using the Fault Injection Debugger x
2.1. Single Event Upset Mitigation 2.2. Hardware and Software Requirements 2.3. Using the Fault Injection Debugger and IP Core 2.4. Document Revision History
2.3. Using the Fault Injection Debugger and IP Core x
2.3.1. Instantiating the IP Core 2.3.2. Defining Fault Injection Areas 2.3.3. Using the Fault Injection Debugger 2.3.4. Command-Line Interface
2.3.1. Instantiating the IP Core x
2.3.1.1. About the EMR Unloader IP Core 2.3.1.2. About the Advanced SEU Detection IP Core
2.3.2. Defining Fault Injection Areas x
2.3.2.1. Performing Hierarchy Tagging 2.3.2.2. About SMH Files
2.3.3. Using the Fault Injection Debugger x
2.3.3.1. Configuring Your Device and the Fault Injection Debugger 2.3.3.2. Constraining Regions for Fault Injection 2.3.3.3. Specifying Error Types 2.3.3.4. Injecting Errors 2.3.3.5. Recording Errors 2.3.3.6. Clearing Injected Errors
2.3.4. Command-Line Interface x
2.3.4.1. Targeted Fault Injection Feature 2.3.4.2. Advanced Command-Line Options: ASD Regions and Error Type Weighting
2.3.4.1. Targeted Fault Injection Feature x
2.3.4.1.1. Specifying an Error List From the Command Line 2.3.4.1.2. Specifying an Error List From Prompt Mode 2.3.4.1.3. Determining CRAM Bit Locations
1. Mitigating Single Event Upset
2. Debugging Single Event Upset Using the Fault Injection Debugger

1.6.2.4. Mitigated FIT

You can lower FIT by reducing the observed FIT rate, such as by enabling ECC. You can also use the optional M20K ECC to mitigate FIT, as well as the (not optional) hard processor ECC and other hard IP such as memory controllers, PCIe, and I/O calibration blocks.

The Projected SEU FIT by Component Usage report's w/ECC column represents the FPGA's lowest guaranteed, provable FIT rate that the Intel® Quartus® Prime software can calculate. ECC does not affect CRAM and flipflop rates; therefore, the data in the w/ECC column for these components is the same as the in Utilized column.

The ECC code strength varies with the device family. In devices, the M20K block can correct up to two errors, and the FIT rate beyond two (not corrected) is small enough to be negligible in the total.

Note: In Cyclone® V devices, the M10K block does not have ECC, therefore, the w/ECC column does not apply.

An MLAB is simply a LAB configured with writable CRAM. However, when the Intel® Quartus® Prime software configures the RAM as write enabled (MLAB), the MLAB has a slightly different FIT/Mb. The Projected SEU FIT by Component Usage report displays a FIT rate in the MLAB row when the design uses MLABs, otherwise the report accounts for the block's FIT in the CRAM row. During compilation, if the Intel® Quartus® Prime software changes a LAB to an MLAB, the FIT accounting moves from the LAB row to the MLAB row.

The w/ECC column does not account for other forms of FIT protection in the design, such as designer-inserted parity, soft ECC blocks, bounds checking, system monitors, triple-module redundancy, or the impact of higher-level protocols on general fault tolerance. Additionally, it does not account for single event effects that occur in the logic but the design never reads or notices. For example, if you implement a non-ECC FIFO function 512 bits deep and an SEU event occurs outside of the front and back pointers, the application does not observe the SEU event. However, the report accounts for the full 512 bit deep memory and includes it in the w/ECC FIT rate. Designers often combine these factors into general deflation factors (called architectural vulnerability factors or AVF) based on knowledge of their design. Designers use AVF factors as low (aggressive) as 5% and as high (conservative) as 50% based on experience, fault-injection or neutron beam testing, or high-level system monitors.

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