1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
22.214.171.124. Performing Hierarchy Tagging
You define the FPGA regions for testing by assigning an ASD Region to the location. You can specify an ASD Region value for any portion of your design hierarchy using the Design Partitions Window.
- Choose Assignments > Design Partitions Window.
- Right-click anywhere in the header row and turn on ASD Region to display the ASD Region column (if it is not already displayed).
- Enter a value from 0 to 16 for any partition to assign it to a specific ASD Region.
- ASD region 0 is reserved to unused portions of the device. You can assign a partition to this region to specify it as non-critical..
- ASD region 1 is the default region. All used portions of the device are assigned to this region unless you explicitly change the ASD Region assignment.
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