AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

ID 683869
Date 9/28/2021
Document Table of Contents Performing Hierarchy Tagging

You define the FPGA regions for testing by assigning an ASD Region to the location. You can specify an ASD Region value for any portion of your design hierarchy using the Design Partitions Window.

  1. Choose Assignments > Design Partitions Window.
  2. Right-click anywhere in the header row and turn on ASD Region to display the ASD Region column (if it is not already displayed).
  3. Enter a value from 0 to 16 for any partition to assign it to a specific ASD Region.
    • ASD region 0 is reserved to unused portions of the device. You can assign a partition to this region to specify it as non-critical..
    • ASD region 1 is the default region. All used portions of the device are assigned to this region unless you explicitly change the ASD Region assignment.