1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
1.5.3. Advanced SEU Detection IP Core
To correct and detect SEU in the FPGA CRAM, you must instantiate the Advanced SEU Detection IP core. When the FPGA's EDCRC detects an SEU, the Advanced SEU Detection IP core looks up the sensitivity of the affected bit in the .smh file.
- During system operation, the Advanced SEU Detection IP core reads the FPGA's error message register (EMR) to determine the location of the error.
- The IP core finds the upset location in the .smh file.
- The IP core returns whether or not the bit is critical for the design.
You can implement either an on-chip or external sensitivity processor:
- On-chip sensitivity processor: the IP core looks up the bit sensitivity in the .smh with a user-supplied memory interface.
- External sensitivity processor: the IP core notifies external logic (typically via a system CPU interrupt request), and provides cached event message register values to the off-chip sensitivity processor. The external sensitivity processor's memory system stores the .smh information.
The Advanced SEU Detection IP Core User Guide provides instructions for incorporating the IP core into your design, and describes how to access the .smh file.
On-Chip Sensitivity Processor
External Sensitivity Processor
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