AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

ID 683869
Date 9/28/2021
Public
Document Table of Contents

1.5.3.2. External Sensitivity Processor

When you implement an external sensitivity processor, a CPU (such as the ARM processor in Intel SoC devices) receives an interrupt request when the FPGA detects an SEU. The CPU then reads the FPGA's error message register and looks up the bit sensitivity in the .smh stored in the CPU's memory space.

With external sensitivity processing, the FPGA does not need to implement an external memory interface or store the .smh. If the system already has a CPU, external sensitivity processing may be more hardware efficient than on-chip processing.

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