1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
1.2.1. Configuring RAM to Enable ECC
To enable ECC, configure the RAM as a 2-port RAM with independent read and write addresses. Using this feature does not reduce the available logic.
Although the ECC checking function results in some additional output delay, the hard ECC has a much higher fMAX compared with an equivalent soft ECC block implemented in general logic. Additionally, you can pipeline the hard IP in the M20K block by configuring the ECC-enabled RAM to use an output register at the corrected data output port. This implementation increases performance and adds latency.For devices without dedicated circuitry, you can implement ECC by instantiating the ALTECC IP core, which performs ECC generation and checking functions.
Memory Storage and ECC
Did you find the information on this page useful?