AN 866: Mitigating and Debugging Single Event Upsets in Intel® Quartus® Prime Standard Edition

Download PDF
ID 683869
Date 9/28/2021
Public
Document Table of Contents
Document Table of Contents x
1. Mitigating Single Event Upset 2. Debugging Single Event Upset Using the Fault Injection Debugger
1. Mitigating Single Event Upset x
1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
1.2. Mitigating SEU Effects in Embedded User RAM x
1.2.1. Configuring RAM to Enable ECC
1.5. SEU Recovery x
1.5.1. Planning for SEU Recovery 1.5.2. Designating the Sensitivity of the Design Hierarchy 1.5.3. Advanced SEU Detection IP Core
1.5.2. Designating the Sensitivity of the Design Hierarchy x
1.5.2.1. Hierarchy Tagging 1.5.2.2. Using Partitions to Specify Logic Sensitivity ID
1.5.3. Advanced SEU Detection IP Core x
1.5.3.1. On-Chip Sensitivity Processor 1.5.3.2. External Sensitivity Processor
1.6. Intel® Quartus® Prime Software SEU FIT Reports x
1.6.1. SEU FIT Parameters Report 1.6.2. Projected SEU FIT by Component Usage Report 1.6.3. Enabling the Projected SEU FIT by Component Usage Report
1.6.2. Projected SEU FIT by Component Usage Report x
1.6.2.1. Component FIT Rates 1.6.2.2. Raw FIT 1.6.2.3. Utilized FIT 1.6.2.4. Mitigated FIT 1.6.2.5. Architectural Vulnerability Factor
1.6.2.3. Utilized FIT x
1.6.2.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 1.6.2.3.2. Considerations for Small Designs
2. Debugging Single Event Upset Using the Fault Injection Debugger x
2.1. Single Event Upset Mitigation 2.2. Hardware and Software Requirements 2.3. Using the Fault Injection Debugger and IP Core 2.4. Document Revision History
2.3. Using the Fault Injection Debugger and IP Core x
2.3.1. Instantiating the IP Core 2.3.2. Defining Fault Injection Areas 2.3.3. Using the Fault Injection Debugger 2.3.4. Command-Line Interface
2.3.1. Instantiating the IP Core x
2.3.1.1. About the EMR Unloader IP Core 2.3.1.2. About the Advanced SEU Detection IP Core
2.3.2. Defining Fault Injection Areas x
2.3.2.1. Performing Hierarchy Tagging 2.3.2.2. About SMH Files
2.3.3. Using the Fault Injection Debugger x
2.3.3.1. Configuring Your Device and the Fault Injection Debugger 2.3.3.2. Constraining Regions for Fault Injection 2.3.3.3. Specifying Error Types 2.3.3.4. Injecting Errors 2.3.3.5. Recording Errors 2.3.3.6. Clearing Injected Errors
2.3.4. Command-Line Interface x
2.3.4.1. Targeted Fault Injection Feature 2.3.4.2. Advanced Command-Line Options: ASD Regions and Error Type Weighting
2.3.4.1. Targeted Fault Injection Feature x
2.3.4.1.1. Specifying an Error List From the Command Line 2.3.4.1.2. Specifying an Error List From Prompt Mode 2.3.4.1.3. Determining CRAM Bit Locations
1. Mitigating Single Event Upset
2. Debugging Single Event Upset Using the Fault Injection Debugger

1.6.2. Projected SEU FIT by Component Usage Report

The Projected SEU FIT by Component Usage report shows the different components (or cell types) that comprise the total FIT rate, and SEU FIT calculation results.

An Intel FPGA's sensitivity to soft errors varies by process technology, component type, and your design choices when implementing the component (such as tradeoffs between area/delay and SEU rates). The report shows all bits (the raw FIT), utilized bits (only resources the design actually uses), and the ECC-mitigated bits.

Figure 6. Projected SEU FIT by Component Usage Report

Section Content
Component FIT Rates
Raw FIT
Utilized FIT
Mitigated FIT
Architectural Vulnerability Factor

Level Two Title