1.1. Failure Rates 1.2. Mitigating SEU Effects in Embedded User RAM 1.3. Mitigating SEU Effects in Configuration RAM 1.4. Internal Scrubbing 1.5. SEU Recovery 1.6. Intel® Quartus® Prime Software SEU FIT Reports 1.7. Triple-Module Redundancy 1.8. Evaluating a System's Response to Functional Upsets 1.9. CRAM Error Detection Settings Reference 1.10. Document Revision History
1.5. SEU Recovery
After correcting a CRAM bit flip, the FPGA is in its original configuration with respect to logic and routing. However, the FPGA may have an illegal internal state, for example, if the SEU error affects the function or operation of the circuit, resulting in erroneous output.
Errors due to faulty operation can propagate elsewhere within the FPGA or to the system outside the FPGA. During your design process, determine the possible SEU outcomes and design a recovery response that considers resetting the FPGA to a known state.
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