AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.6. Viewing the Results

Perform the followings steps to confirm the link for JESD204B instances 0 and 1 up successfully.

  1. In the Nios® II console, you should observe it reports no pattern check error detected on JESD204B instances 0 and 1 (subsystem 0 in HDL) shown in the following figure. You can refer to Table 1 and Table 2 for the expected value of TX/RX status 0 registers for JESD204B instances 0 and 1.
    Figure 2. Pass or Fail Indication in Nios® II Console
  2. You should observe LEDs D3-D7 illuminate while LEDs D8-D10 off after successful bring up the links.
    Figure 3. On-Board User LED
    Table 6.  Reference Design Status LED on the Intel® Arria® 10 GX Development Kit
    LED Board Reference Signal Name Description
    D3 frame_rst_n Transport layer, test pattern generator and checker reset signal. The LED illuminates to indicate that the transport layer, test pattern generator and checker are out of reset.
    D4 link_rst_n JESD204B IP cores link layer, transport layer link interfaces reset signal. The LED illuminates to indicate that the JESD204B IP cores link layer, and transport layer link interfaces are out of reset.
    D5 sync_n SYNC_N from the JESD204B IP cores receiver. The LED illuminates to indicate it successfully received K28.5 characters.
    D6 alldev_lane_aligned All lanes align signal for JESD204B IP cores instance 0 and 1. The LED illuminates to indicate all lanes are aligned.
    D7 rx_dev_sync_n_out Single AND SYNC~ signals from JESD204B IP cores instance 0 and 1 to the transmitter. The LED illuminates to indicate that the transmitter has received sufficient K28.5 characters.
    D8 jesd204_rx_int The link layer RX interrupt status signal from both JESD204B IP cores instance 0 & 1. The LED illuminates to indicate a RX interrupt.
    D9 jesd204_tx_int The link layer TX interrupt status signal from both JESD204B IP cores instance 0 & 1. The LED illuminates to indicate a TX interrupt.
    D10 avst_patchk_data_error Single AND error status signal for PRBS, RAMP or ATL checkers for JESD204B IP cores instance 0 & 1. The LED illuminates to indicate a data error.
  3. You can also observe the behavior of frame_rst_n, link_rst_n, sync_n, alldev_lane_aligned, rx_dev_sync_n, jesd204_rx_int, jesd204_tx_int and avst_pathchk_data_error signals through Signal Tap file to verify the links up successfully.
    Figure 4. Example of the Expected Signal Tap Waveform (rx_link instance)
    In the output receiver transport layer, expect to see the PRBS, RAMP, ALT pattern based on the pattern source defined in main.h file.
    Figure 5. Example of the Expected Signal Tap Waveform (trpt instance) For example, you should see the pattern as indicated in the following figure if you set the SOURCEDEST_INIT in main.h file as RAMP pattern.
    Figure 6. Link Latency Measurement for RBD offset=5Latency of link measured between transmitter and receiver in this design. The link latency is measured from rising edge of jesd204_tx_link_ready signal to rising edge of jesd204_rx_link_valid signal.
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