AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.5.2. Rebuilding Software and Initializing the JESD204B Link

Perform the following steps to rebuild Nios® II software, re-execute the software C code and initialize the JESD204B link:

  1. After device programming, navigate to the Tools menu and select Nios® II Software Build Tools for Eclipse.
  2. In the Select a workspace dialog box, navigate to the software workspace, <project directory>/software and click OK.
  3. On the File menu, navigate to New and click Nios® II Application and BSP From Template.
  4. In the Nios II Application and BSP From Template window, enter the following information:
    1. SOPC Information File Name:
      • Intel® Quartus® Prime Pro Edition: <project directory>/jesd204b_ed_qsys/jesd204b_ed_qsys.sopcinfo
      • Intel® Quartus® Prime Standard Edition: <project directory>/jesd204b_ed_qsys.sopcinfo
    2. Project name: jesd204b_nios2_ed
      Note: Project name is user customizable.
    3. User default location: Checked
    4. Templates: Blank Project
  5. Click Next. Verify that the default BSP name is jesd204b_nios2_ed_bsp and click Finish. The Nios® II application project (jesd204b_nios2_ed) and BSP (jesd204b_nios2_ed_bsp) appears in the Project Explorer window.
    Note: Whenever you regenerate the jesd204b_ed_qsys.qsys, you must regenerate the BSP files. In the Project Explorer window, right click the jesd204b_nios2_ed_bsp project, navigate to Nios II and click Generate BSP. This regenerates the BSP files based on your most current jesd204b_ed_qsys.sopcinfo.
  6. Import the design example source (*.c) and header (*.h) files into the application directory. In the Project Explorer window, right click on the jesd204b_nios2_ed project and click Import.
  7. In the Import window, select General > File System as the import source. Click Next.
  8. Browse to the <project directory>/software/source directory and click OK. Check the source box on the left panel. Verify that the list of source and header files are as follows:
    • altera_jesd204_regs.h
    • functions.h
    • macros.h
    • macros.c
    • main.h
    • main.c
  9. Verify that the destination folder is jesd204b_nios2_ed. Click Finish. All the source and header files should be imported into the jesd204b_nios2_ed project directory.
  10. Right click the jesd204b_nios2_ed_bsp project, navigate to Nios II and click BSP Editor. Under the Drivers tab, check the enable_small_driver box of the altera_avalon_jtag_uart_driver group and click Generate. This setting allows the compilation to proceed without connecting the interrupt ports of JTAG UART module. After the BSP files have been generated, click Exit.
  11. Expand the jesd204b_nios2_ed application project in the Project Explorer window and verify that folder contains all the source and header files.
  12. To compile the C code, navigate to the Project menu and select Build all. The compiler now compiles the C code into executable code.
  13. To download the executable code to the development board, right click on the jesd204b_nios2_ed in Project Explorer window and select Run As and then Nios II Hardware.
  14. Refer to Table 3 to change SOURCEDEST_INIT parameter if you want to test other supported pattern. Change the LOOPBACK_INIT parameter to 1 if you want test internal serial loopback. Next, repeat 12 to 13.
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